ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.S

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
index 2f4be7e93f54495c31ee37a2ec9130f1e49d1f3b..7fb454c3dde45d836b6b6b473bd76e44f98470b2 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2011, ARM Limited. All rights reserved.\r
@@ -73,12 +73,12 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
   bx lr\r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           \r
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     \r
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
   bx      lr\r
 \r
 \r
@@ -135,7 +135,7 @@ ASM_PFX(ArmEnableDataCache):
   orr     R0,R0,R1              @Set C bit\r
   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
   bx      LR\r
-    \r
+\r
 ASM_PFX(ArmDisableDataCache):\r
   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON\r
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
@@ -149,7 +149,7 @@ ASM_PFX(ArmEnableInstructionCache):
   orr     R0,R0,R1             @Set I bit\r
   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDisableInstructionCache):\r
   ldr     R1,=IC_ON\r
   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data\r
@@ -171,17 +171,17 @@ ASM_PFX(ArmDisableBranchPrediction):
 \r
 ASM_PFX(ArmDataMemoryBarrier):\r
   mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #5 \r
+  mcr P15, #0, R0, C7, C10, #5\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDataSyncronizationBarrier):\r
   mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #4 \r
+  mcr P15, #0, R0, C7, C10, #4\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmInstructionSynchronizationBarrier):\r
   mov R0, #0\r
-  mcr P15, #0, R0, C7, C5, #4 \r
+  mcr P15, #0, R0, C7, C5, #4\r
   bx      LR\r
 \r
 ASM_PFX(ArmSetLowVectors):\r
@@ -206,7 +206,7 @@ ASM_PFX(ArmIsMpCore):
   cmp     r0, r1\r
   movne   r0, #0\r
   pop     { r1 }\r
-  bx      lr     \r
+  bx      lr\r
 \r
 ASM_PFX(ArmCallWFI):\r
   wfi\r