ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.S

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
index 28cc5b6e6c33e03ca6011f30921985c642a8c050..c708d212a9a8e6d582510cee5b4387bc3c9a45ec 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 #\r
@@ -41,11 +41,11 @@ GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
 #------------------------------------------------------------------------------\r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line                                           \r
+  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line     \r
+  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
@@ -58,17 +58,17 @@ ASM_PFX(ArmEnableInstructionCache):
   orr    r0,r0,r1             @Set I bit\r
   mcr    p15,0,r0,c1,c0,0     @Write control register configuration data\r
   bx     LR\r
-  \r
+\r
 ASM_PFX(ArmDisableInstructionCache):\r
   ldr    r1,=IC_ON\r
   mrc    p15,0,r0,c1,c0,0     @Read control register configuration data\r
   bic    r0,r0,r1             @Clear I bit.\r
   mcr    p15,0,r0,c1,c0,0     @Write control register configuration data\r
   bx     LR\r
-  \r
+\r
 ASM_PFX(ArmInvalidateInstructionCache):\r
   mov     r0,#0\r
-  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache. \r
+  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache.\r
                          @Also flushes the branch target cache.\r
   mov     r0,#0\r
   mcr     p15,0,r0,c7,c10,4    @Data write buffer\r
@@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
   orr     R0,R0,R1              @Set C bit\r
   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDisableDataCache):\r
   ldr     R1,=DC_ON\r
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
@@ -113,7 +113,7 @@ ASM_PFX(ArmCleanDataCache):
   mov     R0,#0\r
   mcr     p15,0,R0,c7,c10,4  @Drain write buffer\r
   bx      LR\r
-    \r
+\r
 ASM_PFX(ArmInvalidateDataCache):\r
   mov     R0,#0\r
   mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache\r
@@ -138,12 +138,12 @@ ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0\r
   mcr P15, #0, R0, C7, C10, #5    @ check if this is OK?\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDataSyncronizationBarrier):\r
   mov R0, #0\r
   mcr P15, #0, R0, C7, C10, #4   @ check if this is OK?\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmInstructionSynchronizationBarrier):\r
   mov R0, #0\r
   mcr P15, #0, R0, C7, C5, #4     @ check if this is OK?\r