#------------------------------------------------------------------------------
#
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
-# All rights reserved. This program and the accompanying materials
+# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#------------------------------------------------------------------------------
+#include <AsmMacroIoLib.h>
+
.text
.align 2
-.globl ASM_PFX(Cp15IdCode)
-.globl ASM_PFX(Cp15CacheInfo)
-.globl ASM_PFX(ArmEnableInterrupts)
-.globl ASM_PFX(ArmDisableInterrupts)
-.globl ASM_PFX(ArmGetInterruptState)
-.globl ASM_PFX(ArmInvalidateTlb)
-.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmSetDomainAccessControl)
-.globl ASM_PFX(CPSRMaskInsert)
-.globl ASM_PFX(CPSRRead)
+
+GCC_ASM_EXPORT(Cp15IdCode)
+GCC_ASM_EXPORT(Cp15CacheInfo)
+GCC_ASM_EXPORT(ArmIsMPCore)
+GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
+GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
+GCC_ASM_EXPORT(ArmEnableIrq)
+GCC_ASM_EXPORT(ArmDisableIrq)
+GCC_ASM_EXPORT(ArmGetInterruptState)
+GCC_ASM_EXPORT(ArmEnableFiq)
+GCC_ASM_EXPORT(ArmDisableFiq)
+GCC_ASM_EXPORT(ArmEnableInterrupts)
+GCC_ASM_EXPORT(ArmDisableInterrupts)
+GCC_ASM_EXPORT(ArmGetFiqState)
+GCC_ASM_EXPORT(ArmInvalidateTlb)
+GCC_ASM_EXPORT(ArmSetTTBR0)
+GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
+GCC_ASM_EXPORT(ArmSetDomainAccessControl)
+GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
+GCC_ASM_EXPORT(CPSRMaskInsert)
+GCC_ASM_EXPORT(CPSRRead)
+GCC_ASM_EXPORT(ReadCCSIDR)
+GCC_ASM_EXPORT(ReadCLIDR)
+
+
#------------------------------------------------------------------------------
mrc p15,0,R0,c0,c0,1
bx LR
+ASM_PFX(ArmIsMPCore):
+ mrc p15,0,R0,c0,c0,5
+ // Get Multiprocessing extension (bit31) & U bit (bit30)
+ and R0, R0, #0xC0000000
+ // if bit30 == 0 then the processor is part of a multiprocessor system)
+ and R0, R0, #0x80000000
+ bx LR
+
+ASM_PFX(ArmEnableAsynchronousAbort):
+ cpsie a
+ isb
+ bx LR
+
+ASM_PFX(ArmDisableAsynchronousAbort):
+ cpsid a
+ isb
+ bx LR
+
+ASM_PFX(ArmEnableIrq):
+ cpsie i
+ isb
+ bx LR
+
+ASM_PFX(ArmDisableIrq):
+ cpsid i
+ isb
+ bx LR
+
+ASM_PFX(ArmGetInterruptState):
+ mrs R0,CPSR
+ tst R0,#0x80 @Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ASM_PFX(ArmEnableFiq):
+ cpsie f
+ isb
+ bx LR
+
+ASM_PFX(ArmDisableFiq):
+ cpsid f
+ isb
+ bx LR
+
ASM_PFX(ArmEnableInterrupts):
- mrs R0,CPSR
- bic R0,R0,#0x80 @Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+ cpsie if
+ isb
+ bx LR
ASM_PFX(ArmDisableInterrupts):
- mrs R0,CPSR
- orr R1,R0,#0x80 @Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
+ cpsid if
+ isb
+ bx LR
+
+ASM_PFX(ArmGetFiqState):
+ mrs R0,CPSR
+ tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
- bx LR
-
-ASM_PFX(ArmGetInterruptState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+ bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
+ isb
bx lr
-ASM_PFX(ArmSetTranslationTableBaseAddress):
+ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
+ isb
bx lr
-ASM_PFX(ArmGetTranslationTableBaseAddress):
+ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
+ LoadConstantToReg(0xFFFFC000, r1)
+ and r0, r0, r1
+ isb
bx lr
ASM_PFX(ArmSetDomainAccessControl):
mcr p15,0,r0,c3,c0,0
+ isb
+ bx lr
+
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+// IN VOID *TranslationTableEntry // R0
+// IN VOID *MVA // R1
+// );
+ASM_PFX(ArmUpdateTranslationTableEntry):
+ mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
+ dsb
+ mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
+ isb
bx lr
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
+ isb
mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
mrs r0, cpsr
bx lr
+// UINT32
+// ReadCCSIDR (
+// IN UINT32 CSSELR
+// )
+ASM_PFX(ReadCCSIDR):
+ mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
+ isb
+ mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
+ bx lr
+
+// UINT32
+// ReadCLIDR (
+// IN UINT32 CSSELR
+// )
+ASM_PFX(ReadCLIDR):
+ mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
+ bx lr
+
ASM_FUNCTION_REMOVE_IF_UNREFERENCED