ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Lib.c

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
index 65709780edaa4508cced8c85c28270ed18efe8ed..feb60881bdcd401d4a78c32c245f481b2be69912 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
@@ -2,7 +2,7 @@
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-  \r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -47,7 +47,7 @@ ArmDataCachePresent (
   )\r
 {\r
   UINT32 CLIDR = ReadCLIDR ();\r
-  \r
+\r
   if ((CLIDR & 0x2) == 0x2) {\r
     // Instruction cache exists\r
     return TRUE;\r
@@ -56,10 +56,10 @@ ArmDataCachePresent (
     // Unified cache\r
     return TRUE;\r
   }\r
-  \r
+\r
   return FALSE;\r
 }\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
 ArmDataCacheSize (\r
@@ -70,15 +70,15 @@ ArmDataCacheSize (
   UINT32 Associativity;\r
   UINT32 LineSize;\r
   UINT32 CCSIDR = ReadCCSIDR (0);\r
-  \r
+\r
   LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
 \r
   // LineSize is in words (4 byte chunks)\r
-  return  NumSets * Associativity * LineSize * 4;      \r
+  return  NumSets * Associativity * LineSize * 4;\r
 }\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
 ArmDataCacheAssociativity (\r
@@ -89,14 +89,14 @@ ArmDataCacheAssociativity (
 \r
   return ((CCSIDR >> 3) & 0x3ff) + 1;\r
 }\r
-  \r
+\r
 UINTN\r
 ArmDataCacheSets (\r
   VOID\r
   )\r
 {\r
   UINT32 CCSIDR = ReadCCSIDR (0);\r
-  \r
+\r
   return ((CCSIDR >> 13) & 0x7fff) + 1;\r
 }\r
 \r
@@ -111,7 +111,7 @@ ArmDataCacheLineLength (
   // * 4 converts to bytes\r
   return (1 << (CCSIDR + 2)) * 4;\r
 }\r
-  \r
+\r
 BOOLEAN\r
 EFIAPI\r
 ArmInstructionCachePresent (\r
@@ -119,7 +119,7 @@ ArmInstructionCachePresent (
   )\r
 {\r
   UINT32 CLIDR = ReadCLIDR ();\r
-  \r
+\r
   if ((CLIDR & 1) == 1) {\r
     // Instruction cache exists\r
     return TRUE;\r
@@ -128,10 +128,10 @@ ArmInstructionCachePresent (
     // Unified cache\r
     return TRUE;\r
   }\r
-  \r
+\r
   return FALSE;\r
 }\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
 ArmInstructionCacheSize (\r
@@ -142,15 +142,15 @@ ArmInstructionCacheSize (
   UINT32 Associativity;\r
   UINT32 LineSize;\r
   UINT32 CCSIDR = ReadCCSIDR (1);\r
-  \r
+\r
   LineSize      = (1 << ((CCSIDR & 0x7) + 2));\r
   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r
   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;\r
 \r
   // LineSize is in words (4 byte chunks)\r
-  return  NumSets * Associativity * LineSize * 4;      \r
+  return  NumSets * Associativity * LineSize * 4;\r
 }\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
 ArmInstructionCacheAssociativity (\r
@@ -162,7 +162,7 @@ ArmInstructionCacheAssociativity (
   return ((CCSIDR >> 3) & 0x3ff) + 1;\r
 //  return 4;\r
 }\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
 ArmInstructionCacheSets (\r
@@ -170,7 +170,7 @@ ArmInstructionCacheSets (
   )\r
 {\r
   UINT32 CCSIDR = ReadCCSIDR (1);\r
-  \r
+\r
   return ((CCSIDR >> 13) & 0x7fff) + 1;\r
 }\r
 \r
@@ -198,11 +198,11 @@ ArmV7DataCacheOperation (
 \r
   SavedInterruptState = ArmGetInterruptState ();\r
   ArmDisableInterrupts ();\r
-  \r
+\r
   ArmV7AllDataCachesOperation (DataCacheOperation);\r
-  \r
+\r
   ArmDrainWriteBuffer ();\r
-  \r
+\r
   if (SavedInterruptState) {\r
     ArmEnableInterrupts ();\r
   }\r
@@ -218,11 +218,11 @@ ArmV7PoUDataCacheOperation (
 \r
   SavedInterruptState = ArmGetInterruptState ();\r
   ArmDisableInterrupts ();\r
-  \r
+\r
   ArmV7PerformPoUDataCacheOperation (DataCacheOperation);\r
-  \r
+\r
   ArmDrainWriteBuffer ();\r
-  \r
+\r
   if (SavedInterruptState) {\r
     ArmEnableInterrupts ();\r
   }\r