ArmPkg/ArmLib: Removed ArmInvalidateTlb when disabling cache as ArmDisableMmu() alrea...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Mmu.c

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index f57e48b3a5ad32c42de0a73e4caad65dbecff2c6..7881a9b9fae2215473a95c94e5e8415f20ad787c 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -1,7 +1,7 @@
 /** @file\r
 *  File managing the MMU for ARMv7 architecture\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *  \r
 *  This program and the accompanying materials                          \r
 *  are licensed and made available under the terms and conditions of the BSD License         \r
@@ -41,19 +41,19 @@ PopulateLevel2PageTable (
 \r
   switch (Attributes) {\r
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
       break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r
       break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r
       break;\r
     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
       PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r
       break;\r
     default:\r
@@ -146,16 +146,16 @@ FillTranslationTable (
     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
       break;\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
       break;\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
       break;\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
       Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
       break;\r
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:\r
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
       break;\r
     default:\r
@@ -214,7 +214,7 @@ ArmConfigureMmu (
     *TranslationTableBase = (VOID *)TranslationTable;\r
   }\r
   \r
-  if (TranslationTableBase != NULL) {\r
+  if (TranslationTableSize != NULL) {\r
     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r
   }\r
 \r
@@ -222,10 +222,10 @@ ArmConfigureMmu (
 \r
   ArmCleanInvalidateDataCache ();\r
   ArmInvalidateInstructionCache ();\r
-  ArmInvalidateTlb ();\r
 \r
   ArmDisableDataCache ();\r
   ArmDisableInstructionCache();\r
+  // TLBs are also invalidated when calling ArmDisableMmu()\r
   ArmDisableMmu ();\r
 \r
   // Make sure nothing sneaked into the cache\r
@@ -235,7 +235,7 @@ ArmConfigureMmu (
   TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
   while (MemoryTable->Length != 0) {\r
     // Find the memory attribute for the Translation Table\r
-    if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {\r
+    if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
       TranslationTableAttribute = MemoryTable->Attributes;\r
     }\r
 \r
@@ -245,20 +245,20 @@ ArmConfigureMmu (
 \r
   // Translate the Memory Attributes into Translation Table Register Attributes\r
   if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || \r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {\r
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
     TTBRAttributes = TTBR_NON_CACHEABLE;\r
   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || \r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {\r
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
     TTBRAttributes = TTBR_WRITE_BACK_ALLOC;\r
   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || \r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {\r
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
     TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;\r
   } else {\r
     //TODO: We should raise an error here\r
     TTBRAttributes = TTBR_NON_CACHEABLE;\r
   }\r
 \r
-  ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));\r
+  ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r
     \r
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
                              DOMAIN_ACCESS_CONTROL_NONE(14) |\r