-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
GCC_ASM_EXPORT (ArmSetLowVectors)\r
GCC_ASM_EXPORT (ArmSetHighVectors)\r
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
+GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
+GCC_ASM_EXPORT (ArmReadVBar)\r
GCC_ASM_EXPORT (ArmWriteVBar)\r
GCC_ASM_EXPORT (ArmEnableVFP)\r
GCC_ASM_EXPORT (ArmCallWFI)\r
\r
\r
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line \r
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
dsb\r
isb\r
bx lr\r
\r
ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line \r
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
dsb\r
isb\r
bx lr\r
\r
\r
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line \r
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r
dsb\r
isb\r
bx lr\r
\r
\r
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line \r
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r
dsb\r
isb\r
bx lr\r
\r
\r
ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line \r
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r
dsb\r
isb\r
bx lr\r
ASM_PFX(ArmMmuEnabled):\r
mrc p15,0,R0,c1,c0,0\r
and R0,R0,#1\r
- bx LR \r
+ bx LR\r
\r
ASM_PFX(ArmEnableDataCache):\r
ldr R1,=DC_ON\r
dsb\r
isb\r
bx LR\r
- \r
+\r
ASM_PFX(ArmDisableDataCache):\r
ldr R1,=DC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
dsb\r
isb\r
bx LR\r
- \r
+\r
ASM_PFX(ArmDisableInstructionCache):\r
ldr R1,=IC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
\r
ASM_PFX(ArmSetHighVectors):\r
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 @ clear V bit\r
+ orr r0, r0, #0x00002000 @ Set V bit\r
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
beq L_Finished\r
mov R10, #0\r
\r
-Loop1: \r
+Loop1:\r
add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
and R12, R12, #7 @ get those 3 bits alone\r
cmp R12, #2\r
blt L_Skip @ no cache or only instruction cache at this level\r
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb @ isb to sync the change to the CacheSizeID reg \r
+ isb @ isb to sync the change to the CacheSizeID reg\r
mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
and R2, R12, #0x7 @ extract the line length field\r
add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
sub R7, R7, #1\r
ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
\r
-Loop2: \r
+Loop2:\r
mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
\r
-Loop3: \r
+Loop3:\r
orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
orr R0, R0, R7, LSL R2 @ factor in the index number\r
\r
bge Loop3\r
subs R7, R7, #1 @ decrement the index\r
bge Loop2\r
-L_Skip: \r
+L_Skip:\r
add R10, R10, #2 @ increment the cache number\r
cmp R3, R10\r
bgt Loop1\r
- \r
+\r
L_Finished:\r
dsb\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
+ASM_PFX(ArmV7PerformPoUDataCacheOperation):\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 @ Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
+ ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU)\r
+ mov R3, R3, LSR #26 @ Cache level value (naturally aligned)\r
+ beq Finished2\r
+ mov R10, #0\r
+\r
+Loop4:\r
+ add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 @ get those 3 bits alone\r
+ cmp R12, #2\r
+ blt Skip2 @ no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb @ isb to sync the change to the CacheSizeID reg\r
+ mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #0x7 @ extract the line length field\r
+ add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
+ ldr R4, =0x3FF\r
+ ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 @ R5 is the bit position of the way size increment\r
+ ldr R7, =0x00007FFF\r
+ ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
+\r
+Loop5:\r
+ mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
+\r
+Loop6:\r
+ orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 @ factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 @ decrement the way number\r
+ bge Loop6\r
+ subs R7, R7, #1 @ decrement the index\r
+ bge Loop5\r
+Skip2:\r
+ add R10, R10, #2 @ increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop4\r
+\r
+Finished2:\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
ASM_PFX(ArmDataMemoryBarrier):\r
dmb\r
bx LR\r
- \r
+\r
ASM_PFX(ArmDataSyncronizationBarrier):\r
ASM_PFX(ArmDrainWriteBuffer):\r
dsb\r
bx LR\r
- \r
+\r
ASM_PFX(ArmInstructionSynchronizationBarrier):\r
isb\r
bx LR\r
\r
+ASM_PFX(ArmReadVBar):\r
+ # Set the Address of the Vector Table in the VBAR register\r
+ mrc p15, 0, r0, c12, c0, 0\r
+ bx lr\r
+\r
ASM_PFX(ArmWriteVBar):\r
# Set the Address of the Vector Table in the VBAR register\r
- mcr p15, 0, r0, c12, c0, 0 \r
+ mcr p15, 0, r0, c12, c0, 0\r
# Ensure the SCTLR.V bit is clear\r
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00002000 @ clear V bit\r
orr r0, r0, #0x00f00000\r
# Write back CPACR (Coprocessor Access Control Register)\r
mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
mov r0, #0x40000000\r
mcr p10,#0x7,r0,c8,c0,#0\r
ASM_PFX(ArmReadMpidr):\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
- \r
+\r
ASM_PFX(ArmReadTpidrurw):\r
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
bx lr\r
projects / mirror_edk2.git / blobdiff