ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 4808c7ba748015fb00e77fe0838e7c182990bc27..368138933a356fdddec7ebc3951c11a685227eef 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
 //\r
 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
@@ -63,13 +63,13 @@ CTRL_I_BIT      EQU     (1 << 12)
 \r
 \r
 ArmInvalidateDataCacheEntryByMVA\r
-  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line       \r
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 ArmCleanDataCacheEntryByMVA\r
-  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     \r
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
   dsb\r
   isb\r
   bx      lr\r
@@ -83,21 +83,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
 \r
 \r
 ArmInvalidateDataCacheEntryBySetWay\r
-  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line    \r
+  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 \r
 ArmCleanInvalidateDataCacheEntryBySetWay\r
-  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line    \r
+  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
   dsb\r
   isb\r
   bx      lr\r
 \r
 \r
 ArmCleanDataCacheEntryBySetWay\r
-  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line    \r
+  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
   dsb\r
   isb\r
   bx      lr\r
@@ -150,7 +150,7 @@ ArmEnableDataCache
   dsb\r
   isb\r
   bx      LR\r
-    \r
+\r
 ArmDisableDataCache\r
   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
@@ -168,7 +168,7 @@ ArmEnableInstructionCache
   dsb\r
   isb\r
   bx      LR\r
-  \r
+\r
 ArmDisableInstructionCache\r
   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
@@ -223,14 +223,14 @@ ArmV7AllDataCachesOperation
   beq   Finished\r
   mov   R10, #0\r
 \r
-Loop1   \r
+Loop1\r
   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
   and   R12, R12, #7            ; get those 3 bits alone\r
   cmp   R12, #2\r
   blt   Skip                    ; no cache or only instruction cache at this level\r
   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           ; isb to sync the change to the CacheSizeID reg \r
+  isb                           ; isb to sync the change to the CacheSizeID reg\r
   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
   and   R2, R12, #&7            ; extract the line length field\r
   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
@@ -240,10 +240,10 @@ Loop1
   ldr   R7, =0x00007FFF\r
   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
 \r
-Loop2   \r
+Loop2\r
   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
 \r
-Loop3   \r
+Loop3\r
   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
   orr   R0, R0, R7, LSL R2      ; factor in the index number\r
 \r
@@ -253,11 +253,11 @@ Loop3
   bge   Loop3\r
   subs  R7, R7, #1              ; decrement the index\r
   bge   Loop2\r
-Skip  \r
+Skip\r
   add   R10, R10, #2            ; increment the cache number\r
   cmp   R3, R10\r
   bgt   Loop1\r
-  \r
+\r
 Finished\r
   dsb\r
   ldmfd SP!, {r4-r12, lr}\r
@@ -272,14 +272,14 @@ ArmV7PerformPoUDataCacheOperation
   beq   Finished2\r
   mov   R10, #0\r
 \r
-Loop4   \r
+Loop4\r
   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
   and   R12, R12, #7            ; get those 3 bits alone\r
   cmp   R12, #2\r
   blt   Skip2                   ; no cache or only instruction cache at this level\r
   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           ; isb to sync the change to the CacheSizeID reg \r
+  isb                           ; isb to sync the change to the CacheSizeID reg\r
   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
   and   R2, R12, #&7            ; extract the line length field\r
   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
@@ -289,10 +289,10 @@ Loop4
   ldr   R7, =0x00007FFF\r
   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
 \r
-Loop5   \r
+Loop5\r
   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
 \r
-Loop6   \r
+Loop6\r
   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
   orr   R0, R0, R7, LSL R2      ; factor in the index number\r
 \r
@@ -302,11 +302,11 @@ Loop6
   bge   Loop6\r
   subs  R7, R7, #1              ; decrement the index\r
   bge   Loop5\r
-Skip2  \r
+Skip2\r
   add   R10, R10, #2            ; increment the cache number\r
   cmp   R3, R10\r
   bgt   Loop4\r
-  \r
+\r
 Finished2\r
   dsb\r
   ldmfd SP!, {r4-r12, lr}\r
@@ -315,12 +315,12 @@ Finished2
 ArmDataMemoryBarrier\r
   dmb\r
   bx      LR\r
-  \r
+\r
 ArmDataSyncronizationBarrier\r
 ArmDrainWriteBuffer\r
   dsb\r
   bx      LR\r
-  \r
+\r
 ArmInstructionSynchronizationBarrier\r
   isb\r
   bx      LR\r
@@ -332,7 +332,7 @@ ArmReadVBar
 \r
 ArmWriteVBar\r
   // Set the Address of the Vector Table in the VBAR register\r
-  mcr     p15, 0, r0, c12, c0, 0 \r
+  mcr     p15, 0, r0, c12, c0, 0\r
   // Ensure the SCTLR.V bit is clear\r
   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
   bic     r0, r0, #0x00002000   ; clear V bit\r