ArmPkg/ArmLib: move cache maintenance sync barriers out of loop

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index f16dd4a4ab01897e737747dafb4f0bffd222a163..d6f249038a053314079d1ab8f37b78f1a5a9cde3 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -62,42 +62,30 @@ CTRL_I_BIT      EQU     (1 << 12)
 \r
 ArmInvalidateDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ArmCleanDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanInvalidateDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmInvalidateDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanInvalidateDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r