ArmPkg: Configure TTBCR register

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / Arm / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index f3b949565f187a44517787c731458bd5e0fd1327..5d1194e7e219ea6dec4b69191383ca693dc1c635 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -1,7 +1,7 @@
-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,12 +15,6 @@
 \r
 #include <AsmMacroIoLib.h>\r
 \r
-#ifdef ARM_CPU_ARMv6\r
-// No memory barriers for ARMv6\r
-#define isb\r
-#define dsb\r
-#endif\r
-\r
 .text\r
 .align 2\r
 GCC_ASM_EXPORT(ArmReadMidr)\r
@@ -29,6 +23,7 @@ GCC_ASM_EXPORT(ArmGetInterruptState)
 GCC_ASM_EXPORT(ArmGetFiqState)\r
 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
 GCC_ASM_EXPORT(ArmSetTTBR0)\r
+GCC_ASM_EXPORT(ArmSetTTBCR)\r
 GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r
 GCC_ASM_EXPORT(CPSRMaskInsert)\r
 GCC_ASM_EXPORT(CPSRRead)\r
@@ -47,6 +42,8 @@ GCC_ASM_EXPORT(ArmWriteHVBar)
 GCC_ASM_EXPORT(ArmCallWFE)\r
 GCC_ASM_EXPORT(ArmCallSEV)\r
 GCC_ASM_EXPORT(ArmReadSctlr)\r
+GCC_ASM_EXPORT(ArmReadCpuActlr)\r
+GCC_ASM_EXPORT(ArmWriteCpuActlr)\r
 \r
 #------------------------------------------------------------------------------\r
 \r
@@ -108,13 +105,18 @@ ASM_PFX(ArmWriteAuxCr):
 \r
 ASM_PFX(ArmReadAuxCr):\r
   mrc     p15, 0, r0, c1, c0, 1\r
-  bx      lr  \r
+  bx      lr\r
 \r
 ASM_PFX(ArmSetTTBR0):\r
   mcr     p15,0,r0,c2,c0,0\r
   isb\r
   bx      lr\r
 \r
+ASM_PFX(ArmSetTTBCR):\r
+  mcr     p15, 0, r0, c2, c0, 2\r
+  isb\r
+  bx      lr\r
+\r
 ASM_PFX(ArmGetTTBR0BaseAddress):\r
   mrc     p15,0,r0,c2,c0,0\r
   LoadConstantToReg(0xFFFFC000, r1)\r
@@ -131,7 +133,7 @@ ASM_PFX(ArmGetTTBR0BaseAddress):
 ASM_PFX(ArmUpdateTranslationTableEntry):\r
   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA\r
   dsb\r
-  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA  \r
+  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA\r
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
   dsb\r
   isb\r
@@ -151,6 +153,7 @@ ASM_PFX(ArmReadScr):
 \r
 ASM_PFX(ArmWriteScr):\r
   mcr     p15, 0, r0, c1, c1, 0\r
+  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmReadHVBar):\r
@@ -161,7 +164,6 @@ ASM_PFX(ArmWriteHVBar):
   mcr     p15, 4, r0, c12, c0, 0\r
   bx      lr\r
 \r
-\r
 ASM_PFX(ArmReadMVBar):\r
   mrc     p15, 0, r0, c12, c0, 1\r
   bx      lr\r
@@ -179,7 +181,17 @@ ASM_PFX(ArmCallSEV):
   bx      lr\r
 \r
 ASM_PFX(ArmReadSctlr):\r
-  mrc     p15, 0, R0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)\r
-  bx     lr\r
+  mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)\r
+  bx      lr\r
+\r
+ASM_PFX(ArmReadCpuActlr):\r
+  mrc     p15, 0, r0, c1, c0, 1\r
+  bx      lr\r
+\r
+ASM_PFX(ArmWriteCpuActlr):\r
+  mcr     p15, 0, r0, c1, c0, 1\r
+  dsb\r
+  isb\r
+  bx      lr\r
 \r
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r