#/** @file\r
#\r
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
# This program and the accompanying materials\r
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
# Stack for CPU Cores in Secure Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r
\r
## PL061 GPIO\r
gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
\r
[PcdsFixedAtBuild.ARM]\r
# Stack for CPU Cores in Secure Monitor Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
\r
[PcdsFixedAtBuild.AARCH64]\r
# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
# and PcdCPUCoreSecSecondaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
\r