/*++\r
\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
-Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR> \r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
#define EB_GIC5_DIST_BASE 0x10071000\r
\r
// number of interrupts sources supported by each GIC on the EB\r
-#define EB_NUM_GIC_INTERRUPTS 96 \r
+#define EB_NUM_GIC_INTERRUPTS 96\r
\r
// number of 32-bit registers needed to represent those interrupts as a bit\r
// (used for enable set, enable clear, pending set, pending clear, and active regs)\r
if (Source > EB_NUM_GIC_INTERRUPTS) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
- } \r
- \r
+ }\r
+\r
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
{\r
UINT32 RegOffset;\r
UINTN RegShift;\r
- \r
+\r
if (Source > EB_NUM_GIC_INTERRUPTS) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
// calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
RegShift = Source % 32;\r
\r
// write set-enable register\r
MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset), 1 << RegShift);\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
{\r
UINT32 RegOffset;\r
UINTN RegShift;\r
- \r
+\r
if (Source > EB_NUM_GIC_INTERRUPTS) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
// calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
RegShift = Source % 32;\r
\r
// write set-enable register\r
MmioWrite32 (EB_GIC1_DIST_BASE+GIC_ICDICER+(4*RegOffset), 1 << RegShift);\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
{\r
UINT32 RegOffset;\r
UINTN RegShift;\r
- \r
+\r
if (Source > EB_NUM_GIC_INTERRUPTS) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
// calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
RegShift = Source % 32;\r
- \r
+\r
if ((MmioRead32 (EB_GIC1_DIST_BASE+GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) {\r
*InterruptState = FALSE;\r
} else {\r
*InterruptState = TRUE;\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Signal to the hardware that the End Of Intrrupt state \r
+ Signal to the hardware that the End Of Intrrupt state\r
has been reached.\r
\r
@param This Instance pointer for this protocol\r
if (GicInterrupt >= EB_NUM_GIC_INTERRUPTS) {\r
MmioWrite32 (EB_GIC1_CPU_INTF_BASE+GIC_ICCEIOR, GicInterrupt);\r
}\r
- \r
+\r
InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
if (InterruptHandler != NULL) {\r
// Call the registered interrupt handler.\r
\r
/**\r
Shutdown our hardware\r
- \r
+\r
DXE Core will disable interrupts and turn off the timer and disable interrupts\r
after all the event handlers have run.\r
\r
)\r
{\r
UINTN i;\r
- \r
+\r
for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
}\r
{\r
EFI_STATUS Status;\r
EFI_CPU_ARCH_PROTOCOL *Cpu;\r
- \r
+\r
//\r
// Get the cpu protocol that this driver requires.\r
//\r
UINT32 RegOffset;\r
UINTN RegShift;\r
\r
- \r
+\r
// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
for (i = 0; i < EB_NUM_GIC_INTERRUPTS; i++) {\r
DisableInterruptSource (&gHardwareInterruptProtocol, i);\r
- \r
- // Set Priority \r
+\r
+ // Set Priority\r
RegOffset = i / 4;\r
RegShift = (i % 4) * 8;\r
MmioAndThenOr32 (\r
- EB_GIC1_DIST_BASE+GIC_ICDIPR+(4*RegOffset), \r
- ~(0xff << RegShift), \r
+ EB_GIC1_DIST_BASE+GIC_ICDIPR+(4*RegOffset),\r
+ ~(0xff << RegShift),\r
GIC_DEFAULT_PRIORITY << RegShift\r
);\r
}\r
\r
// set priority mask reg to 0xff to allow all priorities through\r
MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCPMR, 0xff);\r
- \r
+\r
// enable gic cpu interface\r
MmioWrite32 (EB_GIC1_CPU_INTF_BASE + GIC_ICCICR, 0x1);\r
\r
// enable gic distributor\r
MmioWrite32 (EB_GIC1_DIST_BASE + GIC_ICCICR, 0x1);\r
\r
- \r
+\r
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));\r
- \r
+\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&gHardwareInterruptHandle,\r
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
// Set up to be notified when the Cpu protocol is installed.\r
- Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent); \r
+ Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent);\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = gBS->RegisterProtocolNotify (&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);\r
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