#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
+// Number of Virtual Memory Map Descriptors without a Logic Tile\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
+\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-#define DDR_ATTRIBUTES_SECURE_CACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_SECURE_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
-\r
-/**\r
- Return the information about the memory region in permanent memory used by PEI\r
-\r
- One of the PEI Module must install the permament memory used by PEI. This function returns the\r
- information about this region for your platform to this PEIM module.\r
-\r
- @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules\r
- @param[out] PeiMemorySize Size of the memory region used by PEI core and modules\r
-\r
-**/\r
-VOID ArmPlatformGetPeiMemory (\r
- OUT UINTN* PeiMemoryBase,\r
- OUT UINTN* PeiMemorySize\r
- ) {\r
- ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));\r
- \r
- *PeiMemoryBase = ARM_VE_DRAM_BASE + ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
- *PeiMemorySize = ARM_VE_EFI_MEMORY_REGION_SZ;\r
-}\r
\r
/**\r
Return the Virtual Memory Map of your platform\r
entry\r
\r
**/\r
-VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
- UINT32 val32;\r
- UINT32 CacheAttributes;\r
- BOOLEAN bTrustzoneSupport;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT(VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.\r
- // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case\r
- val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);\r
- if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {\r
- bTrustzoneSupport = TRUE;\r
- } else {\r
- bTrustzoneSupport = FALSE;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
- } else {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
- }\r
-\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT(VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {\r
// ReMap (Either NOR Flash or DRAM)\r
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMC CS7\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS0-CS1 - NOR Flash 1 & 2\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS2 - SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMB CS3-CS6 - Motherboard Peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
- if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+ }\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // SMC CS7\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS0-CS1 - NOR Flash 1 & 2\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS2 - SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // SMB CS3-CS6 - Motherboard Peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+ if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
+ } else {\r
+ ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
+ }\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
}\r
\r
/**\r
- Return the EFI Memory Map of your platform\r
+ Return the EFI Memory Map provided by extension memory on your platform\r
\r
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
Descriptor HOBs used by DXE core.\r
EFI Memory region. This array must be ended by a zero-filled entry\r
\r
**/\r
-VOID ArmPlatformGetEfiMemoryMap (\r
- OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
-) {\r
- EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
- UINT64 MemoryBase;\r
- UINTN Index = 0;\r
- ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR *EfiMemoryTable;\r
-\r
- ASSERT(EfiMemoryMap != NULL);\r
-\r
- EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);\r
-\r
- Attributes =\r
- (\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED\r
- );\r
- MemoryBase = ARM_VE_DRAM_BASE;\r
- \r
- // Memory Reserved for fixed address allocations (such as Exception Vector Table)\r
- EfiMemoryTable[Index].ResourceAttribute = Attributes;\r
- EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
- \r
- MemoryBase += ARM_VE_EFI_FIX_ADDRESS_REGION_SZ;\r
-\r
- // Memory declared to PEI as permanent memory for PEI and DXE\r
- EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
- EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = ARM_VE_EFI_MEMORY_REGION_SZ;\r
-\r
- MemoryBase += ARM_VE_EFI_MEMORY_REGION_SZ;\r
-\r
- // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000\r
- if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
- // Chunk between the EFI Memory region and the firmware\r
- EfiMemoryTable[++Index].ResourceAttribute = Attributes;\r
- EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdBaseAddress) - MemoryBase;\r
-\r
- // Chunk reserved by the firmware in DRAM\r
- EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);\r
- EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdNormalFdBaseAddress);\r
- EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdSize);\r
-\r
- MemoryBase = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize);\r
- }\r
- \r
- // We allocate all the remain memory as untested system memory\r
- EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);\r
- EfiMemoryTable[Index].PhysicalStart = MemoryBase;\r
- EfiMemoryTable[Index].NumberOfBytes = ARM_VE_DRAM_SZ - (MemoryBase-ARM_VE_DRAM_BASE);\r
-\r
- EfiMemoryTable[++Index].ResourceAttribute = 0;\r
- EfiMemoryTable[Index].PhysicalStart = 0;\r
- EfiMemoryTable[Index].NumberOfBytes = 0;\r
-\r
- *EfiMemoryMap = EfiMemoryTable;\r
+EFI_STATUS\r
+ArmPlatformGetAdditionalSystemMemory (\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
}\r
projects / mirror_edk2.git / blobdiff