#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
+// Number of Virtual Memory Map Descriptors without a Logic Tile\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
+\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-#define DDR_ATTRIBUTES_SECURE_CACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_SECURE_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED\r
\r
/**\r
Return the Virtual Memory Map of your platform\r
entry\r
\r
**/\r
-VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
- UINT32 val32;\r
- UINT32 CacheAttributes;\r
- BOOLEAN bTrustzoneSupport;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT(VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.\r
- // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case\r
- val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);\r
- if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {\r
- bTrustzoneSupport = TRUE;\r
- } else {\r
- bTrustzoneSupport = FALSE;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
- } else {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
- }\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT(VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
\r
+ if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {\r
// ReMap (Either NOR Flash or DRAM)\r
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMC CS7\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS0-CS1 - NOR Flash 1 & 2\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS2 - SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMB CS3-CS6 - Motherboard Peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
- if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+ }\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // SMC CS7\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS0-CS1 - NOR Flash 1 & 2\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS2 - SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // SMB CS3-CS6 - Motherboard Peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+ if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
+ } else {\r
+ ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
+ }\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
}\r
\r
/**\r
- Return the EFI Memory Map of your platform\r
+ Return the EFI Memory Map provided by extension memory on your platform\r
\r
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
Descriptor HOBs used by DXE core.\r
projects / mirror_edk2.git / blobdiff