/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <ArmPlatform.h>\r
\r
-// Number of Virtual Memory Map Descriptors without a Logic Tile\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5\r
+// Number of Virtual Memory Map Descriptors\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
)\r
{\r
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
UINTN Index = 0;\r
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT(VirtualMemoryMap != NULL);\r
+ UINT32 SysId;\r
+ BOOLEAN HasSparseMemory;\r
+ EFI_VIRTUAL_ADDRESS SparseMemoryBase;\r
+ UINT64 SparseMemorySize;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ // The FVP model has Sparse memory\r
+ SysId = MmioRead32 (ARM_VE_SYS_ID_REG);\r
+ if (SysId != ARM_RTSM_SYS_ID) {\r
+ HasSparseMemory = TRUE;\r
+\r
+ ResourceAttributes =\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED;\r
+\r
+ // Declared the additional DRAM from 2GB to 4GB\r
+ SparseMemoryBase = 0x0880000000;\r
+ SparseMemorySize = SIZE_2GB;\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ ResourceAttributes,\r
+ SparseMemoryBase,\r
+ SparseMemorySize);\r
+ } else {\r
+ HasSparseMemory = FALSE;\r
+ SparseMemoryBase = 0x0;\r
+ SparseMemorySize = 0x0;\r
+ }\r
\r
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
if (VirtualMemoryTable == NULL) {\r
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
// SMB CS0-CS1 - NOR Flash 1 & 2\r
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
// SMB CS2 - SRAM\r
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
-\r
-//TODO:This should be enabled for final release. Right now, ARM VE RTSM crashes.\r
-// // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
-// if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
-// VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
-// VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
-// VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
-// VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;\r
-//\r
-// ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
-// } else {\r
-// ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
-// }\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // Map sparse memory region if present\r
+ if (HasSparseMemory) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r
+ VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;\r
+ VirtualMemoryTable[Index].Length = SparseMemorySize;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+ }\r
\r
// End of Table\r
VirtualMemoryTable[++Index].PhysicalBase = 0;\r
\r
*VirtualMemoryMap = VirtualMemoryTable;\r
}\r
-\r
-/**\r
- Return the EFI Memory Map provided by extension memory on your platform\r
-\r
- This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
- Descriptor HOBs used by DXE core.\r
- TODO: CompleteMe .... say this is the memory not covered by the System Memory PCDs\r
-\r
- @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
- EFI Memory region. This array must be ended by a zero-filled entry\r
-\r
-**/\r
-EFI_STATUS\r
-ArmPlatformGetAdditionalSystemMemory (\r
- OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
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