ArmPlatformPkg: Added initial support for the FVP Base and Foundation Models

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressSecLibRTSM / AArch64 / GicV3.S

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
new file mode 100644 (file)
index 0000000..8d2bde2
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
@@ -0,0 +1,67 @@
+//\r
+//  Copyright (c) 2013, ARM Limited. All rights reserved.\r
+//\r
+//  This program and the accompanying materials\r
+//  are licensed and made available under the terms and conditions of the BSD License\r
+//  which accompanies this distribution.  The full text of the license may be found at\r
+//  http://opensource.org/licenses/bsd-license.php\r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+// Register definitions used by GCC for GICv3 access.\r
+// These are defined by ARMCC, so keep them in the GCC specific code for now.\r
+#define ICC_SRE_EL2     S3_4_C12_C9_5\r
+#define ICC_SRE_EL3     S3_6_C12_C12_5\r
+#define ICC_CTLR_EL1    S3_0_C12_C12_4\r
+#define ICC_CTLR_EL3    S3_6_C12_C12_4\r
+#define ICC_PMR_EL1     S3_0_C4_C6_0\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(InitializeGicV3)\r
+\r
+/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
+ASM_PFX(InitializeGicV3):\r
+  // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup\r
+  // to allow Linux to use GICv3 if it chooses.\r
+\r
+  // In order to setup NS side we need to enable it first.\r
+  mrs     x0, scr_el3\r
+  orr     x0, x0, #1\r
+  msr     scr_el3, x0\r
+\r
+  // Enable SRE at EL3 and ICC_SRE_EL2 access\r
+  mov     x0, #((1 << 3) | (1 << 0))      // Enable | SRE\r
+  mrs     x1, ICC_SRE_EL3\r
+  orr     x1, x1, x0\r
+  msr     ICC_SRE_EL3, x1\r
+  isb\r
+\r
+  // Enable SRE at EL2 and ICC_SRE_EL1 access..\r
+  mrs     x1, ICC_SRE_EL2\r
+  orr     x1, x1, x0\r
+  msr     ICC_SRE_EL2, x1\r
+  isb\r
+\r
+  // Configure CPU interface\r
+  msr     ICC_CTLR_EL3, xzr\r
+  isb\r
+  msr     ICC_CTLR_EL1, xzr\r
+  isb\r
+\r
+  // The MemoryMap view and Register view may not be consistent, So Set PMR again.\r
+  mov     w1, #1 << 7                        // allow NS access to GICC_PMR\r
+  msr     ICC_PMR_EL1, x1\r
+  isb\r
+\r
+  // Remove the SCR.NS bit\r
+  mrs     x0, scr_el3\r
+  bic     x0, x0, #1\r
+  msr     scr_el3, x0\r
+  ret\r