Serial I/O Port library functions with no library constructor/destructor\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
- \r
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include <Drivers/PL011Uart.h>\r
\r
-/*\r
+#define FRACTION_PART_SIZE_IN_BITS 6\r
+#define FRACTION_PART_MASK ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)\r
+\r
+//\r
+// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only\r
+// control bit that is not supported.\r
+//\r
+STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
+\r
+/**\r
\r
Initialise the serial port to the specified settings.\r
All unspecified settings will be set to the default values.\r
\r
- @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.\r
+ @param UartBase The base address of the serial device.\r
+ @param BaudRate The baud rate of the serial device. If the\r
+ baud rate is not supported, the speed will be\r
+ reduced to the nearest supported one and the\r
+ variable's value will be updated accordingly.\r
+ @param ReceiveFifoDepth The number of characters the device will\r
+ buffer on input. Value of 0 will use the\r
+ device's default FIFO depth.\r
+ @param Parity If applicable, this is the EFI_PARITY_TYPE\r
+ that is computed or checked as each character\r
+ is transmitted or received. If the device\r
+ does not support parity, the value is the\r
+ default parity value.\r
+ @param DataBits The number of data bits in each character.\r
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
+ of stop bits per character.\r
+ If the device does not support stop bits, the\r
+ value is the default stop bit value.\r
+\r
+ @retval RETURN_SUCCESS All attributes were set correctly on the\r
+ serial device.\r
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
+ unsupported value.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartInitializePort (\r
- IN UINTN UartBase,\r
- IN UINT64 BaudRate,\r
- IN UINT32 ReceiveFifoDepth,\r
- IN UINT32 Timeout,\r
- IN EFI_PARITY_TYPE Parity,\r
- IN UINT8 DataBits,\r
- IN EFI_STOP_BITS_TYPE StopBits\r
+ IN UINTN UartBase,\r
+ IN OUT UINT64 *BaudRate,\r
+ IN OUT UINT32 *ReceiveFifoDepth,\r
+ IN OUT EFI_PARITY_TYPE *Parity,\r
+ IN OUT UINT8 *DataBits,\r
+ IN OUT EFI_STOP_BITS_TYPE *StopBits\r
)\r
{\r
UINT32 LineControl;\r
UINT32 Divisor;\r
\r
- // The BaudRate must be passed\r
- if (BaudRate == 0) {\r
- return RETURN_INVALID_PARAMETER;\r
- }\r
- \r
LineControl = 0;\r
\r
- // The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept\r
- // 1 char buffer as the minimum fifo size. Because everything can be rounded down,\r
- // there is no maximum fifo size.\r
- if (ReceiveFifoDepth == 0) {\r
- LineControl |= PL011_UARTLCR_H_FEN;\r
- } else if (ReceiveFifoDepth < 32) {\r
- // Nothing else to do. 1 byte fifo is default.\r
- } else if (ReceiveFifoDepth >= 32) {\r
+ // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept\r
+ // 1 char buffer as the minimum FIFO size. Because everything can be rounded\r
+ // down, there is no maximum FIFO size.\r
+ if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) {\r
+ // Enable FIFO\r
LineControl |= PL011_UARTLCR_H_FEN;\r
+ if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4)\r
+ *ReceiveFifoDepth = 32;\r
+ else\r
+ *ReceiveFifoDepth = 16;\r
+ } else {\r
+ ASSERT (*ReceiveFifoDepth < 32);\r
+ // Nothing else to do. 1 byte FIFO is default.\r
+ *ReceiveFifoDepth = 1;\r
}\r
\r
//\r
// Parity\r
//\r
- switch (Parity) {\r
+ switch (*Parity) {\r
case DefaultParity:\r
+ *Parity = NoParity;\r
case NoParity:\r
// Nothing to do. Parity is disabled by default.\r
break;\r
LineControl |= PL011_UARTLCR_H_PEN;\r
break;\r
case MarkParity:\r
- LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS | PL011_UARTLCR_H_EPS);\r
+ LineControl |= ( PL011_UARTLCR_H_PEN \\r
+ | PL011_UARTLCR_H_SPS \\r
+ | PL011_UARTLCR_H_EPS);\r
break;\r
case SpaceParity:\r
LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r
//\r
// Data Bits\r
//\r
- switch (DataBits) {\r
+ switch (*DataBits) {\r
case 0:\r
+ *DataBits = 8;\r
case 8:\r
LineControl |= PL011_UARTLCR_H_WLEN_8;\r
break;\r
//\r
// Stop Bits\r
//\r
- switch (StopBits) {\r
+ switch (*StopBits) {\r
case DefaultStopBits:\r
+ *StopBits = OneStopBit;\r
case OneStopBit:\r
// Nothing to do. One stop bit is enabled by default.\r
break;\r
LineControl |= PL011_UARTLCR_H_STP2;\r
break;\r
case OneFiveStopBits:\r
- // Only 1 or 2 stops bits are supported\r
+ // Only 1 or 2 stop bits are supported\r
default:\r
return RETURN_INVALID_PARAMETER;\r
}\r
- \r
+\r
// Don't send the LineControl value to the PL011 yet,\r
// wait until after the Baud Rate setting.\r
// This ensures we do not mess up the UART settings halfway through\r
//\r
// Baud Rate\r
//\r
- if (PcdGet32(PL011UartInteger) != 0) {\r
- // Integer and Factional part must be different of 0\r
- ASSERT(PcdGet32(PL011UartFractional) != 0);\r
- \r
- MmioWrite32 (UartBase + UARTIBRD, PcdGet32(PL011UartInteger));\r
- MmioWrite32 (UartBase + UARTFBRD, PcdGet32(PL011UartFractional));\r
+\r
+ // If PL011 Integer value has been defined then always ignore the BAUD rate\r
+ if (PcdGet32 (PL011UartInteger) != 0) {\r
+ MmioWrite32 (UartBase + UARTIBRD, PcdGet32 (PL011UartInteger));\r
+ MmioWrite32 (UartBase + UARTFBRD, PcdGet32 (PL011UartFractional));\r
} else {\r
- Divisor = (PcdGet32 (PL011UartClkInHz) * 4) / BaudRate;\r
- MmioWrite32 (UartBase + UARTIBRD, Divisor >> 6);\r
- MmioWrite32 (UartBase + UARTFBRD, Divisor & 0x3F);\r
+ // If BAUD rate is zero then replace it with the system default value\r
+ if (*BaudRate == 0) {\r
+ *BaudRate = PcdGet32 (PcdSerialBaudRate);\r
+ ASSERT (*BaudRate != 0);\r
+ }\r
+\r
+ Divisor = (PcdGet32 (PL011UartClkInHz) * 4) / *BaudRate;\r
+ MmioWrite32 (UartBase + UARTIBRD, Divisor >> FRACTION_PART_SIZE_IN_BITS);\r
+ MmioWrite32 (UartBase + UARTFBRD, Divisor & FRACTION_PART_MASK);\r
}\r
\r
// No parity, 1 stop, no fifo, 8 data bits\r
// Clear any pending errors\r
MmioWrite32 (UartBase + UARTECR, 0);\r
\r
- // Enable tx, rx, and uart overall\r
- MmioWrite32 (UartBase + UARTCR, PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r
+ // Enable Tx, Rx, and UART overall\r
+ MmioWrite32 (UartBase + UARTCR,\r
+ PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r
\r
return RETURN_SUCCESS;\r
}\r
\r
/**\r
- Set the serial device control bits.\r
-\r
- @param UartBase The base address of the PL011 UART.\r
- @param Control Control bits which are to be set on the serial device.\r
\r
- @retval EFI_SUCCESS The new control bits were set on the serial device.\r
- @retval EFI_UNSUPPORTED The serial device does not support this operation.\r
- @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+ Assert or deassert the control signals on a serial port.\r
+ The following control signals are set according their bit settings :\r
+ . Request to Send\r
+ . Data Terminal Ready\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[in] Control The following bits are taken into account :\r
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
+ "Request To Send" control signal if this bit is\r
+ equal to one/zero.\r
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
+ the "Data Terminal Ready" control signal if this\r
+ bit is equal to one/zero.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
+ the hardware loopback if this bit is equal to\r
+ one/zero.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
+ disable the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals.\r
+\r
+ @retval RETURN_SUCCESS The new control bits were set on the device.\r
+ @retval RETURN_UNSUPPORTED The device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
- IN UINTN UartBase,\r
- IN UINT32 Control\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
)\r
{\r
- UINT32 Bits;\r
- UINT32 ValidControlBits;\r
-\r
- ValidControlBits = ( EFI_SERIAL_REQUEST_TO_SEND\r
- | EFI_SERIAL_DATA_TERMINAL_READY\r
- // | EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE // Not implemented yet.\r
- // | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE // Not implemented yet.\r
- | EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE\r
- );\r
-\r
- if (Control & (~ValidControlBits)) {\r
- return EFI_UNSUPPORTED;\r
+ UINT32 Bits;\r
+\r
+ if (Control & (mInvalidControlBits)) {\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
Bits = MmioRead32 (UartBase + UARTCR);\r
\r
if (Control & EFI_SERIAL_REQUEST_TO_SEND) {\r
Bits |= PL011_UARTCR_RTS;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_RTS;\r
}\r
\r
if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {\r
Bits |= PL011_UARTCR_DTR;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_DTR;\r
}\r
\r
if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {\r
Bits |= PL011_UARTCR_LBE;\r
+ } else {\r
+ Bits &= ~PL011_UARTCR_LBE;\r
}\r
\r
if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {\r
- Bits |= (PL011_UARTCR_CTSEN & PL011_UARTCR_RTSEN);\r
+ Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
+ } else {\r
+ Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r
}\r
\r
MmioWrite32 (UartBase + UARTCR, Bits);\r
}\r
\r
/**\r
- Get the serial device control bits.\r
-\r
- @param UartBase The base address of the PL011 UART.\r
- @param Control Control signals read from the serial device.\r
\r
- @retval EFI_SUCCESS The control bits were read from the serial device.\r
- @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+ Retrieve the status of the control bits on a serial device.\r
+\r
+ @param[in] UartBase UART registers base address\r
+ @param[out] Control Status of the control bits on a serial device :\r
+\r
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
+ EFI_SERIAL_DATA_SET_READY,\r
+ EFI_SERIAL_RING_INDICATE,\r
+ EFI_SERIAL_CARRIER_DETECT,\r
+ EFI_SERIAL_REQUEST_TO_SEND,\r
+ EFI_SERIAL_DATA_TERMINAL_READY\r
+ are all related to the DTE (Data Terminal Equipment)\r
+ and DCE (Data Communication Equipment) modes of\r
+ operation of the serial device.\r
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
+ receive buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
+ transmit buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
+ the hardware loopback is enabled (the ouput feeds the\r
+ receive buffer), 0 otherwise.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
+ a loopback is accomplished by software, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
+ one if the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals is\r
+ enabled, 0 otherwise.\r
+\r
+ @retval RETURN_SUCCESS The control bits were read from the serial device.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
- IN UINTN UartBase,\r
- OUT UINT32 *Control\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
)\r
{\r
UINT32 FlagRegister;\r
*Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r
}\r
\r
- if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
+ if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r
+ == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r
}\r
\r
-#ifdef NEVER\r
- // ToDo: Implement EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE\r
if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {\r
*Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;\r
}\r
\r
- // ToDo: Implement EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE\r
- if (SoftwareLoopbackEnable) {\r
- *Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
- }\r
-#endif\r
-\r
return RETURN_SUCCESS;\r
}\r
\r
IN UINTN NumberOfBytes\r
)\r
{\r
- UINTN Count;\r
+ UINT8* CONST Final = &Buffer[NumberOfBytes];\r
\r
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
- while ((MmioRead32 (UartBase + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);\r
- MmioWrite8 (UartBase + UARTDR, *Buffer);\r
- }\r
+ while (Buffer < Final) {\r
+ // Wait until UART able to accept another char\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));\r
\r
- return NumberOfBytes;\r
+ MmioWrite8 (UartBase + UARTDR, *Buffer++);\r
+ }\r
+\r
+ return NumberOfBytes;\r
}\r
\r
/**\r
{\r
UINTN Count;\r
\r
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
- while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r
- *Buffer = MmioRead8 (UartBase + UARTDR);\r
- }\r
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r
+ *Buffer = MmioRead8 (UartBase + UARTDR);\r
+ }\r
\r
- return NumberOfBytes;\r
+ return NumberOfBytes;\r
}\r
\r
/**\r
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