#Maintain 8 byte alignment\r
.align 3\r
\r
+GCC_ASM_EXPORT(PL35xSmcInitialize)\r
\r
-GCC_ASM_EXPORT(SMCInitializeNOR)\r
-GCC_ASM_EXPORT(SMCInitializeSRAM)\r
-GCC_ASM_EXPORT(SMCInitializePeripherals)\r
-GCC_ASM_EXPORT(SMCInitializeVRAM)\r
-\r
-\r
-# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
-# CS1 CS1-Interf0 Reserved for the motherboard\r
-# CS2 CS2-Interf0 SRAM on the motherboard\r
-# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
-# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
-# CS5 CS1-Interf1 memory-mapped peripherals\r
-# CS6 CS2-Interf1 memory-mapped peripherals\r
-# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
-\r
-// IN r1 SmcBase\r
-// IN r2 ChipSelect\r
+// IN r1 Smc Base Address\r
+// IN r2 Smc Configuration Start Address\r
+// IN r3 Smc Configuration End Address\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeNOR):\r
-#\r
-# Setup NOR1 (CS0-Interface0)\r
-#\r
-\r
- # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- #Read cycle timeout = 0xA (0:3)\r
- #Write cycle timeout = 0x3(7:4)\r
- #OE Assertion Delay = 0x9(11:8)\r
- #WE Assertion delay = 0x3(15:12)\r
- #Page cycle timeout = 0x2(19:16) \r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
-\r
- # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- # 0x00000000 = ChipSelect0-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- bx lr\r
-\r
-ASM_PFX(SMCInitializeSRAM):\r
-#\r
-# Setup SRAM (CS2-Interface0)\r
-#\r
- LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
-\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01000000 = ChipSelect2-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
+ASM_PFX(PL35xSmcInitialize):\r
+ // While (SmcConfigurationStart < SmcConfigurationEnd)\r
+ cmp r2, r3\r
+ blxge lr\r
\r
-ASM_PFX(SMCInitializePeripherals):\r
-#\r
-# USB/Eth/VRAM (CS3-Interface0)\r
-#\r
- LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01800000 = ChipSelect3-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+ ldr r0, [r2, #0x4]\r
+ str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
\r
-#\r
-# Setup NOR3 (CS0-Interface1)\r
-#\r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x02000000 = ChipSelect0-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Setup Peripherals (CS3-Interface1)\r
-#\r
- LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x03800000 = ChipSelect3-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- bx lr\r
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+ ldr r0, [r2, #0x8]\r
+ str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
\r
-// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeVRAM):\r
-#\r
-# Setup VRAM (CS1-Interface0)\r
-#\r
- LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x00800000 = ChipSelect1-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Page mode setup for VRAM\r
-#\r
- #read current state \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
+ ldr r4, [r2, #0x0]\r
+ orr r0, r0, r4\r
+ str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
\r
- #enable page mode \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
- str r0, [r2, #0] \r
+ add r2, #0xC\r
+ b ASM_PFX(PL350SmcInitialize)\r
\r
- #confirm page mode enabled\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- \r
- bx lr\r
- \r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file
projects / mirror_edk2.git / blobdiff