/** @file\r
*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
#include <Uefi.h>\r
#include <Protocol/SerialIo.h>\r
\r
+#define PL011_VARIANT_ZTE 1\r
+\r
// PL011 Registers\r
+#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
+#define UARTDR 0x004\r
+#define UARTRSR 0x010\r
+#define UARTECR 0x010\r
+#define UARTFR 0x014\r
+#define UARTIBRD 0x024\r
+#define UARTFBRD 0x028\r
+#define UARTLCR_H 0x030\r
+#define UARTCR 0x034\r
+#define UARTIFLS 0x038\r
+#define UARTIMSC 0x040\r
+#define UARTRIS 0x044\r
+#define UARTMIS 0x048\r
+#define UARTICR 0x04c\r
+#define UARTDMACR 0x050\r
+#else\r
#define UARTDR 0x000\r
#define UARTRSR 0x004\r
#define UARTECR 0x004\r
#define UARTMIS 0x040\r
#define UARTICR 0x044\r
#define UARTDMACR 0x048\r
+#endif\r
+\r
+#define UARTPID0 0xFE0\r
+#define UARTPID1 0xFE4\r
+#define UARTPID2 0xFE8\r
+#define UARTPID3 0xFEC\r
\r
// Data status bits\r
#define UART_DATA_ERROR_MASK 0x0F00\r
#define UART_STATUS_ERROR_MASK 0x0F\r
\r
// Flag reg bits\r
+#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
+#define PL011_UARTFR_RI (1 << 0) // Ring indicator\r
+#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
+#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
+#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
+#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
+#define PL011_UARTFR_BUSY (1 << 8) // UART busy\r
+#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
+#define PL011_UARTFR_DSR (1 << 3) // Data set ready\r
+#define PL011_UARTFR_CTS (1 << 1) // Clear to send\r
+#else\r
#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
+#endif\r
\r
// Flag reg bits - alternative names\r
#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
\r
-/*\r
+#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r
+#define PL011_VER_R1P4 0x2\r
\r
- Programmed hardware of Serial port.\r
+/**\r
\r
- @return Always return EFI_UNSUPPORTED.\r
+ Initialise the serial port to the specified settings.\r
+ All unspecified settings will be set to the default values.\r
+\r
+ @param[in] UartBase The base address of the serial device.\r
+ @param[in] UartClkInHz The clock in Hz for the serial device.\r
+ Ignored if the PCD PL011UartInteger is not 0\r
+ @param[in out] BaudRate The baud rate of the serial device. If the\r
+ baud rate is not supported, the speed will be\r
+ reduced to the nearest supported one and the\r
+ variable's value will be updated accordingly.\r
+ @param[in out] ReceiveFifoDepth The number of characters the device will\r
+ buffer on input. Value of 0 will use the\r
+ device's default FIFO depth.\r
+ @param[in out] Parity If applicable, this is the EFI_PARITY_TYPE\r
+ that is computed or checked as each character\r
+ is transmitted or received. If the device\r
+ does not support parity, the value is the\r
+ default parity value.\r
+ @param[in out] DataBits The number of data bits in each character.\r
+ @param[in out] StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
+ of stop bits per character.\r
+ If the device does not support stop bits, the\r
+ value is the default stop bit value.\r
+\r
+ @retval RETURN_SUCCESS All attributes were set correctly on the\r
+ serial device.\r
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
+ unsupported value.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartInitializePort (\r
- IN OUT UINTN UartBase,\r
+ IN UINTN UartBase,\r
+ IN UINT32 UartClkInHz,\r
IN OUT UINT64 *BaudRate,\r
IN OUT UINT32 *ReceiveFifoDepth,\r
IN OUT EFI_PARITY_TYPE *Parity,\r
disable the hardware flow control based on CTS (Clear\r
To Send) and RTS (Ready To Send) control signals.\r
\r
- @retval RETURN_SUCCESS The new control bits were set on the serial device.\r
- @retval RETURN_UNSUPPORTED The serial device does not support this operation.\r
+ @retval RETURN_SUCCESS The new control bits were set on the device.\r
+ @retval RETURN_UNSUPPORTED The device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
@param[in] UartBase UART registers base address\r
@param[out] Control Status of the control bits on a serial device :\r
\r
- . EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,\r
- EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,\r
- EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY\r
- are all related to the DTE (Data Terminal Equipment) and\r
- DCE (Data Communication Equipment) modes of operation of\r
- the serial device.\r
- . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive\r
- buffer is empty, 0 otherwise.\r
- . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit\r
- buffer is empty, 0 otherwise.\r
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the\r
- hardware loopback is enabled (the ouput feeds the receive\r
- buffer), 0 otherwise.\r
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a\r
- loopback is accomplished by software, 0 otherwise.\r
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the\r
- hardware flow control based on CTS (Clear To Send) and RTS\r
- (Ready To Send) control signals is enabled, 0 otherwise.\r
-\r
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
+ EFI_SERIAL_DATA_SET_READY,\r
+ EFI_SERIAL_RING_INDICATE,\r
+ EFI_SERIAL_CARRIER_DETECT,\r
+ EFI_SERIAL_REQUEST_TO_SEND,\r
+ EFI_SERIAL_DATA_TERMINAL_READY\r
+ are all related to the DTE (Data Terminal Equipment)\r
+ and DCE (Data Communication Equipment) modes of\r
+ operation of the serial device.\r
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
+ receive buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
+ transmit buffer is empty, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
+ the hardware loopback is enabled (the ouput feeds the\r
+ receive buffer), 0 otherwise.\r
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
+ a loopback is accomplished by software, 0 otherwise.\r
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
+ one if the hardware flow control based on CTS (Clear\r
+ To Send) and RTS (Ready To Send) control signals is\r
+ enabled, 0 otherwise.\r
\r
@retval RETURN_SUCCESS The control bits were read from the serial device.\r
\r
/**\r
Check to see if any data is available to be read from the debug device.\r
\r
- @retval EFI_SUCCESS At least one byte of data is available to be read\r
- @retval EFI_NOT_READY No data is available to be read\r
- @retval EFI_DEVICE_ERROR The serial device is not functioning properly\r
+ @retval TRUE At least one byte of data is available to be read\r
+ @retval FALSE No data is available to be read\r
\r
**/\r
BOOLEAN\r
projects / mirror_edk2.git / blobdiff