-/** @file HDLcd.h\r
+/** @file\r
\r
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
**/\r
\r
-#ifndef _HDLCD_H_\r
-#define _HDLCD_H_\r
+#ifndef HDLCD_H_\r
+#define HDLCD_H_\r
\r
-//\r
// HDLCD Controller Register Offsets\r
-//\r
-\r
#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
\r
-\r
-//\r
// HDLCD Values of registers\r
-//\r
\r
// HDLCD Interrupt mask, clear and status register\r
#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */\r
#define HDLCD_DATA_LOW 0\r
#define HDLCD_PXCLK_LOW 0\r
\r
+// Default polarities\r
+#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \\r
+ HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \\r
+ HDLCD_VSYNC_HIGH)\r
+\r
// Pixel Format\r
#define HDLCD_LITTLE_ENDIAN (0 << 31)\r
#define HDLCD_BIG_ENDIAN (1 << 31)\r
// Number of bytes per pixel\r
#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)\r
\r
-#endif /* _HDLCD_H_ */\r
+#endif /* HDLCD_H_ */\r