BaseTools/Capsule: Do not support -o with --dump-info

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / AArch64 / Helper.S

diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
index 8e23b0389653d9efb9797c296f3649698301af24..b4f35b7ff5d389ecf61c025f85bb6cf8fcce793d 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
+++ b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
@@ -1,5 +1,5 @@
 #========================================================================================\r
-#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
 #\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
@@ -14,15 +14,8 @@
 #include <AsmMacroIoLibV8.h>\r
 #include <Chipset/AArch64.h>\r
 \r
-#start of the code section\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(SetupExceptionLevel1)\r
-GCC_ASM_EXPORT(SetupExceptionLevel2)\r
-\r
 // Setup EL1 while in EL1\r
-ASM_PFX(SetupExceptionLevel1):\r
+ASM_FUNC(SetupExceptionLevel1)\r
    mov  x5, x30                   // Save LR\r
 \r
    mov  x0, #CPACR_CP_FULL_ACCESS\r
@@ -31,7 +24,7 @@ ASM_PFX(SetupExceptionLevel1):
    ret  x5\r
 \r
 // Setup EL2 while in EL2\r
-ASM_PFX(SetupExceptionLevel2):\r
+ASM_FUNC(SetupExceptionLevel2)\r
    msr     sctlr_el2, xzr\r
    mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register\r
 \r
@@ -43,6 +36,13 @@ ASM_PFX(SetupExceptionLevel2):
 \r
    msr     cptr_el2, xzr          // Disable copro traps to EL2\r
 \r
+   // Enable Timer access for non-secure EL1 and EL0\r
+   // The cnthctl_el2 register bits are architecturally\r
+   // UNKNOWN on reset.\r
+   // Disable event stream as it is not in use at this stage\r
+   mov     x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)\r
+   msr     cnthctl_el2, x0\r
+\r
    ret\r
 \r
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r