ArmPlatformPkg: Fix stack switch bug after commit 7945b29

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index fdd8697edfffaa407458dc7e1c838dc441afc47e..3a81e2e23f2c77b3c20e5244bd8d6d4557b0ec7b 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -1,15 +1,15 @@
 /** @file\r
 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
@@ -17,23 +17,15 @@
 #include <Library/DebugAgentLib.h>\r
 #include <Library/ArmLib.h>\r
 \r
-#include <Ppi/ArmGlobalVariable.h>\r
-\r
 #include "PrePeiCore.h"\r
 \r
-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI   mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
-ARM_GLOBAL_VARIABLE_PPI             mGlobalVariablePpi = { PrePeiCoreGetGlobalVariableMemory };\r
+CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI   mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI,\r
     &gEfiTemporaryRamSupportPpiGuid,\r
-    &mTemporaryRamSupportPpi\r
-  },\r
-  {\r
-    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
-    &gArmGlobalVariablePpiGuid,\r
-    &mGlobalVariablePpi\r
+    (VOID *) &mTemporaryRamSupportPpi\r
   }\r
 };\r
 \r
@@ -53,7 +45,7 @@ CreatePpiList (
   ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
 \r
   // Copy the Common and Platform PPis in Temporrary Memory\r
-  ListBase = PcdGet32 (PcdCPUCoresStackBase);\r
+  ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
   CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
   CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
 \r
@@ -71,14 +63,13 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-  //Clean Data cache\r
-  ArmCleanInvalidateDataCache ();\r
-\r
-  //Invalidate instruction cache\r
+  // Data Cache enabled on Primary core when MMU is enabled.\r
+  ArmDisableDataCache ();\r
+  // Invalidate Data cache\r
+  ArmInvalidateDataCache ();\r
+  // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
-\r
-  // Enable Instruction & Data caches\r
-  ArmEnableDataCache ();\r
+  // Enable Instruction Caches on all cores.\r
   ArmEnableInstructionCache ();\r
 \r
   //\r
@@ -87,13 +78,15 @@ CEntryPoint (
   //\r
 \r
   // Write VBAR - The Exception Vector table must be aligned to its requirement\r
+  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+  // 'Align=4K' is defined into your FDF for this module.\r
   ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
   ArmWriteVBar ((UINTN)PeiVectorTable);\r
 \r
   //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
 \r
   // If not primary Jump to Secondary Main\r
-  if (IS_PRIMARY_CORE(MpId)) {\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
     // Initialize the Debug Agent for Source Level Debugging\r
     InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
     SaveAndSetDebugTimerInterrupt (TRUE);\r
@@ -124,39 +117,27 @@ PrePeiCoreTemporaryRamSupport (
   VOID                             *NewHeap;\r
   VOID                             *OldStack;\r
   VOID                             *NewStack;\r
+  UINTN                            HeapSize;\r
+\r
+  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r
 \r
   OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
-  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));\r
+  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r
 \r
-  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));\r
+  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r
   NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
 \r
   //\r
   // Migrate the temporary memory stack to permanent memory stack.\r
   //\r
-  CopyMem (NewStack, OldStack, CopySize >> 1);\r
+  CopyMem (NewStack, OldStack, CopySize - HeapSize);\r
 \r
   //\r
   // Migrate the temporary memory heap to permanent memory heap.\r
   //\r
-  CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
-  \r
-  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
+  CopyMem (NewHeap, OldHeap, HeapSize);\r
 \r
-  return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetGlobalVariableMemory (\r
-  OUT EFI_PHYSICAL_ADDRESS    *GlobalVariableBase\r
-  )\r
-{\r
-  ASSERT (GlobalVariableBase != NULL);\r
-\r
-  *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +\r
-                        (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r
-                        (UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r
+  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
 \r
   return EFI_SUCCESS;\r
 }\r
-\r