*\r
**/\r
\r
-#include <PiPei.h>\r
-#include <Ppi/TemporaryRamSupport.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
+#include <Library/PrintLib.h>\r
#include <Library/ArmLib.h>\r
+#include <Library/SerialPortLib.h>\r
#include <Chipset/ArmV7.h>\r
\r
-EFI_STATUS\r
-EFIAPI\r
-SecTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
- );\r
-\r
-VOID\r
-SecSwitchStack (\r
- INTN StackDelta\r
- );\r
+#include "PrePeiCore.h"\r
\r
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r
\r
}\r
};\r
\r
-// Vector Table for Pei Phase\r
-VOID PeiVectorTable (VOID);\r
-\r
-\r
VOID\r
CEntryPoint (\r
IN UINTN CoreId,\r
ArmInvalidateInstructionCache();\r
\r
// Enable Instruction & Data caches\r
- ArmEnableDataCache();\r
- ArmEnableInstructionCache();\r
+ ArmEnableDataCache ();\r
+ ArmEnableInstructionCache ();\r
\r
//\r
// Note: Doesn't have to Enable CPU interface in non-secure world,\r
//If not primary Jump to Secondary Main\r
if(0 == CoreId) {\r
//Goto primary Main.\r
- primary_main(PeiCoreEntryPoint);\r
+ PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
- secondary_main(CoreId);\r
+ SecondaryMain (CoreId);\r
}\r
\r
// PEI Core should always load and never return\r
{\r
//\r
// Migrate the whole temporary memory to permenent memory.\r
- // \r
+ //\r
CopyMem (\r
(VOID*)(UINTN)PermanentMemoryBase, \r
(VOID*)(UINTN)TemporaryMemoryBase, \r