\r
#include "PrePi.h"\r
\r
+#include <Library/ArmGicLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
\r
VOID\r
PrimaryMain (\r
IN UINT64 StartTimeStamp\r
)\r
{\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ // Enable the GIC Distributor\r
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
}\r
\r
PrePiMain (UefiMemoryBase, StartTimeStamp);\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r