ArmPkg/ArmGicLib: Changed ArmGicSendSgiTo() to allow to send a specific SGI

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 165e7cfcb0b3eab02609f24c2ab5af856610079a..e9a3ef56a0046572fb0de32e2865ef6ce8abb586 100644 (file)
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -14,26 +14,61 @@
 \r
 #include "PrePi.h"\r
 \r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+EFI_STATUS\r
+GetPlatformPpi (\r
+  IN  EFI_GUID  *PpiGuid,\r
+  OUT VOID      **Ppi\r
+  )\r
+{\r
+  UINTN                   PpiListSize;\r
+  UINTN                   PpiListCount;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;\r
+  UINTN                   Index;\r
+\r
+  PpiListSize = 0;\r
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+    if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
+      *Ppi = PpiList->Ppi;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
 \r
 VOID\r
 PrimaryMain (\r
   IN  UINTN                     UefiMemoryBase,\r
+  IN  UINTN                     StacksBase,\r
+  IN  UINTN                     GlobalVariableBase,\r
   IN  UINT64                    StartTimeStamp\r
   )\r
 {\r
-  //Enable the GIC Distributor\r
-  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
+  DEBUG_CODE_BEGIN();\r
+    EFI_STATUS              Status;\r
+    ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+\r
+    Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+    ASSERT_EFI_ERROR (Status);\r
+  DEBUG_CODE_END();\r
+\r
+  // Enable the GIC Distributor\r
+  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
-  PrePiMain (UefiMemoryBase, StartTimeStamp);\r
+  PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
 \r
   // We must never return\r
   ASSERT(FALSE);\r
@@ -41,26 +76,53 @@ PrimaryMain (
 \r
 VOID\r
 SecondaryMain (\r
-  IN  UINTN                     CoreId\r
+  IN  UINTN                     MpId\r
   )\r
 {\r
-  // Function pointer to Secondary Core entry point\r
-  VOID (*secondary_start)(VOID);\r
-  UINTN secondary_entry_addr=0;\r
+  EFI_STATUS              Status;\r
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+  UINTN                   Index;\r
+  UINTN                   ArmCoreCount;\r
+  ARM_CORE_INFO           *ArmCoreInfoTable;\r
+  UINT32                  ClusterId;\r
+  UINT32                  CoreId;\r
+  VOID                    (*SecondaryStart)(VOID);\r
+  UINTN                   SecondaryEntryAddr;\r
+\r
+  ClusterId = GET_CLUSTER_ID(MpId);\r
+  CoreId    = GET_CORE_ID(MpId);\r
+\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
+  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  ArmCoreCount = 0;\r
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  // Find the core in the ArmCoreTable\r
+  for (Index = 0; Index < ArmCoreCount; Index++) {\r
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  // The ARM Core Info Table must define every core\r
+  ASSERT (Index != ArmCoreCount);\r
 \r
   // Clear Secondary cores MailBox\r
-  ArmClearMPCoreMailbox();\r
+  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
 \r
-  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
-    ArmCallWFI();\r
+  SecondaryEntryAddr = 0;\r
+  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+    ArmCallWFI ();\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
   }\r
 \r
-  secondary_start = (VOID (*)())secondary_entry_addr;\r
-\r
   // Jump to secondary core entry point.\r
-  secondary_start();\r
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
+  SecondaryStart();\r
 \r
   // The secondaries shouldn't reach here\r
   ASSERT(FALSE);\r