ArmGicSendSgiTo (\r
IN INTN GicDistributorBase,\r
IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
)\r
{\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | PcdGet32(PcdGicSgiIntId));\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
}\r
\r
UINT32\r
#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
[Packages]\r
ArmPkg/ArmPkg.dec\r
MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdGicSgiIntId\r
PcdLib\r
\r
[FixedPcd.common]\r
- gArmTokenSpaceGuid.PcdGicSgiIntId\r
-\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
gArmTokenSpaceGuid.PcdArmPrimaryCore\r
ArmGicSendSgiTo (\r
IN INTN GicDistributorBase,\r
IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
);\r
\r
UINT32\r
/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
if (IS_PRIMARY_CORE(MpId)) {\r
// Signal the secondary cores they can jump to PEI phase\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
\r
// To enter into Non Secure state, we need to make a return from exception\r
*JumpAddress = PcdGet32(PcdFvBaseAddress);\r
[LibraryClasses]
DebugLib
PcdLib
- ArmGicSecLib
+ ArmGicLib
PrintLib
SerialPortLib
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicSgiIntId
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
}\r
\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
#/** @file\r
# Pre PeiCore - Hand-off to PEI Core in Normal World\r
# \r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId\r
/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
}\r
\r
PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
#/** @file\r
# \r
-# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId\r
\r
gArmTokenSpaceGuid.PcdSystemMemoryBase\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r