/** @file\r
-IA32, X64 and IPF Specific relocation fixups\r
+IA32 and X64 Specific relocation fixups\r
\r
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
return RETURN_UNSUPPORTED;\r
}\r
\r
-RETURN_STATUS\r
-PeCoffLoaderRelocateIpfImage (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Performs an Itanium-based specific relocation fixup\r
-\r
-Arguments:\r
-\r
- Reloc - Pointer to the relocation record\r
-\r
- Fixup - Pointer to the address to fix up\r
-\r
- FixupData - Pointer to a buffer to log the fixups\r
-\r
- Adjust - The offset to adjust the fixup\r
-\r
-Returns:\r
-\r
- Status code\r
-\r
---*/\r
-{\r
- UINT64 *F64;\r
- UINT64 FixupVal;\r
-\r
- switch ((*Reloc) >> 12) {\r
-\r
- case EFI_IMAGE_REL_BASED_IA64_IMM64:\r
-\r
- //\r
- // Align it to bundle address before fixing up the\r
- // 64-bit immediate value of the movl instruction.\r
- //\r
-\r
- Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));\r
- FixupVal = (UINT64)0;\r
-\r
- //\r
- // Extract the lower 32 bits of IMM64 from bundle\r
- //\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,\r
- IMM64_IMM41a_SIZE_X,\r
- IMM64_IMM41a_INST_WORD_POS_X,\r
- IMM64_IMM41a_VAL_POS_X\r
- );\r
-\r
- //\r
- // Update 64-bit address\r
- //\r
- FixupVal += Adjust;\r
-\r
- //\r
- // Insert IMM64 into bundle\r
- //\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),\r
- IMM64_IMM41a_SIZE_X,\r
- IMM64_IMM41a_INST_WORD_POS_X,\r
- IMM64_IMM41a_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),\r
- IMM64_IMM41b_SIZE_X,\r
- IMM64_IMM41b_INST_WORD_POS_X,\r
- IMM64_IMM41b_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),\r
- IMM64_IMM41c_SIZE_X,\r
- IMM64_IMM41c_INST_WORD_POS_X,\r
- IMM64_IMM41c_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),\r
- IMM64_SIGN_SIZE_X,\r
- IMM64_SIGN_INST_WORD_POS_X,\r
- IMM64_SIGN_VAL_POS_X\r
- );\r
-\r
- F64 = (UINT64 *) Fixup;\r
- if (*FixupData != NULL) {\r
- *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));\r
- *(UINT64 *)(*FixupData) = *F64;\r
- *FixupData = *FixupData + sizeof(UINT64);\r
- }\r
- break;\r
-\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
\r
/**\r
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and\r