Added support for L2 (4K) page tables and made the CPU driver change cachability...

[mirror_edk2.git] / BeagleBoardPkg / Sec / Cache.c

diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c
index facc5deae40d6c07e7385305abd9e6ddbecea551..d7c906244c5ab21345bd8e22efdb21c1d896c141 100755 (executable)
--- a/BeagleBoardPkg/Sec/Cache.c
+++ b/BeagleBoardPkg/Sec/Cache.c
@@ -58,29 +58,23 @@ InitCache (
   MemoryTable[0].Length       = MemoryLength;\r
   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
 \r
-  // Uncached DDR Mirror\r
-  MemoryTable[1].PhysicalBase = MemoryBase;\r
-  MemoryTable[1].VirtualBase  = MemoryBase | UncachedMemoryMask;\r
-  MemoryTable[1].Length       = MemoryLength;\r
-  MemoryTable[1].Attributes   = DDR_ATTRIBUTES_UNCACHED;\r
-\r
   // SOC Registers. L3 interconnects\r
-  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
-  MemoryTable[2].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
   \r
   // SOC Registers. L4 interconnects\r
-  MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
-  MemoryTable[3].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
 \r
   // End of Table\r
-  MemoryTable[4].PhysicalBase = 0;\r
-  MemoryTable[4].VirtualBase  = 0;\r
-  MemoryTable[4].Length       = 0;\r
-  MemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+  MemoryTable[3].PhysicalBase = 0;\r
+  MemoryTable[3].VirtualBase  = 0;\r
+  MemoryTable[3].Length       = 0;\r
+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
   \r
   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
   \r