| CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
\r
// Set count & reload registers\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
\r
// Disable interrupts\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
\r
// Start Timer\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
\r
//Disable OMAP Watchdog timer (WDT2)\r
- MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
- MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r
}\r
\r
VOID\r
UINT32 UartBaseAddress = UartBase(Uart);\r
\r
// Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r
- MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
+ MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
\r
// Put device in configuration mode.\r
- MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
+ MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
\r
// Programmable divisor N = 48Mhz/16/115200 = 26\r
- MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor\r
- MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
+ MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor\r
+ MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
\r
// Enter into UART operational mode.\r
- MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
+ MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
\r
// Force DTR and RTS output to active\r
- MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
+ MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
\r
// Clear & enable fifos\r
- MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
+ MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
\r
// Restore MODE_SELECT \r
- MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
+ MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
}\r
\r
VOID\r
VOID *HobBase;\r
\r
//Set up Pin muxing.\r
- PadConfiguration();\r
+ PadConfiguration ();\r
\r
// Set up system clocking\r
- ClockInit();\r
+ ClockInit ();\r
\r
// Build a basic HOB list\r
HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r
- CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);\r
+ CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r
\r
// Enable program flow prediction, if supported.\r
- ArmEnableBranchPrediction();\r
+ ArmEnableBranchPrediction ();\r
\r
// Initialize CPU cache\r
- InitCache((UINT32)MemoryBase, (UINT32)MemorySize);\r
+ InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r
\r
// Add memory allocation hob for relocated FD\r
- BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
+ BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
\r
// Add the FVs to the hob list\r
- BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
+ BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
\r
// Start talking\r
- UartInit();\r
- DEBUG((EFI_D_ERROR, "UART Enabled\n"));\r
+ UartInit ();\r
+ DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
\r
DEBUG_CODE_BEGIN ();\r
//\r
}\r
}
- DEBUG_CODE_END ();\r
+ \r
+ DEBUG_CODE_END ();\r
\r
\r
\r
// Start up a free running time so that the timer lib will work\r
- TimerInit();\r
+ TimerInit ();\r
\r
// SEC phase needs to run library constructors by hand.\r
- ExtractGuidedSectionLibConstructor();\r
- LzmaDecompressLibConstructor();\r
+ ExtractGuidedSectionLibConstructor ();\r
+ LzmaDecompressLibConstructor ();\r
\r
// Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
-#if 0\r
BuildPeCoffLoaderHob ();\r
BuildExtractSectionHob (\r
&gLzmaCustomDecompressGuid,\r
LzmaGuidedSectionGetInfo,\r
LzmaGuidedSectionExtraction\r
);\r
-#endif\r
\r
DecompressFirstFv ();\r
\r
// Load the DXE Core and transfer control to it\r
- LoadDxeCoreFromFv(NULL, 0);\r
+ LoadDxeCoreFromFv (NULL, 0);\r
\r
// DXE Core should always load and never return\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r