+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
- VirtualMemory.c\r
- \r
-Abstract:\r
-\r
- x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
- Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
- enter Long Mode (x64 64-bit mode).\r
-\r
- While we make a 1:1 mapping (identity mapping) for all physical pages \r
- we still need to use the MTRR's to ensure that the cachability attirbutes\r
- for all memory regions is correct.\r
-\r
- The basic idea is to use 2MB page table entries where ever possible. If\r
- more granularity of cachability is required then 4K page tables are used.\r
-\r
- References:\r
- 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
- 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
- 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
- \r
---*/ \r
-\r
-#include "VirtualMemory.h"\r
-\r
-x64_MTRR_VARIABLE_RANGE *mMTRRVariableRange;\r
-x64_MTRR_FIXED_RANGE mMTRRFixedRange;\r
-\r
-\r
-//\r
-// Physial memory limit values for each of the 11 fixed MTRRs\r
-//\r
-UINTN mFixedRangeLimit[] = {\r
- 0x7FFFF, // Fixed MTRR #0 describes 0x00000..0x7FFFF\r
- 0x9FFFF, // Fixed MTRR #1 describes 0x80000..0x9FFFF\r
- 0xBFFFF, // Fixed MTRR #2 describes 0xA0000..0xBFFFF\r
- 0xC7FFF, // Fixed MTRR #3 describes 0xC0000..0xC7FFF\r
- 0xCFFFF, // Fixed MTRR #4 describes 0xC8000..0xCFFFF\r
- 0xD7FFF, // Fixed MTRR #5 describes 0xD0000..0xD7FFF\r
- 0xDFFFF, // Fixed MTRR #6 describes 0xD8000..0xDFFFF\r
- 0xE7FFF, // Fixed MTRR #7 describes 0xE0000..0xE7FFF\r
- 0xEFFFF, // Fixed MTRR #8 describes 0xE8000..0xEFFFF\r
- 0xF7FFF, // Fixed MTRR #9 describes 0xF0000..0xF7FFF\r
- 0xFFFFF // Fixed MTRR #10 describes 0xF8000..0xFFFFF\r
-};\r
-\r
-//\r
-// The size, in bits, of each of the 11 fixed MTRR.\r
-//\r
-UINTN mFixedRangeShift[] = {\r
- 16, // Fixed MTRR #0 describes 8, 64 KB ranges\r
- 14, // Fixed MTRR #1 describes 8, 16 KB ranges\r
- 14, // Fixed MTRR #2 describes 8, 16 KB ranges\r
- 12, // Fixed MTRR #3 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #4 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #5 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #6 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #7 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #8 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #9 describes 8, 4 KB ranges\r
- 12 // Fixed MTRR #10 describes 8, 4 KB ranges\r
-};\r
-\r
-\r
-UINTN mPowerOf2[] = {\r
- 1,\r
- 2,\r
- 4,\r
- 8,\r
- 16,\r
- 32,\r
- 64,\r
- 128,\r
- 256,\r
- 512\r
-};\r
-\r
-x64_MTRR_MEMORY_TYPE\r
-EfiGetMTRRMemoryType (\r
- IN EFI_PHYSICAL_ADDRESS Address\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Retrieves the memory type from the MTRR that describes a physical address.\r
-\r
-Arguments:\r
-\r
- VariableRange - Set of Variable MTRRs\r
-\r
- FixedRange - Set of Fixed MTRRs\r
-\r
- Address - The physical address for which the MTRR memory type is being retrieved\r
-\r
-Returns:\r
-\r
- The MTRR Memory Type for the physical memory specified by Address.\r
-\r
---*/\r
-{\r
- UINTN Index;\r
- UINTN TypeIndex;\r
- BOOLEAN Found;\r
- x64_MTRR_MEMORY_TYPE VariableType;\r
- EFI_PHYSICAL_ADDRESS MaskBase;\r
- EFI_PHYSICAL_ADDRESS PhysMask;\r
-\r
- //\r
- // If the MTRRs are disabled, then return the Uncached Memory Type\r
- //\r
- if (mMTRRFixedRange.DefaultType.Bits.E == 0) {\r
- return Uncached;\r
- }\r
-\r
- //\r
- // If the CPU supports Fixed MTRRs and the Fixed MTRRs are enabled, then \r
- // see if Address falls into one of the Fixed MTRRs\r
- //\r
- if (mMTRRFixedRange.Capabilities.Bits.FIX && mMTRRFixedRange.DefaultType.Bits.FE) {\r
- //\r
- // Loop though 11 fixed MTRRs\r
- //\r
- for (Index = 0; Index < 11; Index++) {\r
- //\r
- // Check for a matching range\r
- //\r
- if (Address <= mFixedRangeLimit[Index]) {\r
- //\r
- // Compute the offset address into the MTRR bu subtrating the base address of the MTRR\r
- //\r
- if (Index > 0) {\r
- Address = Address - (mFixedRangeLimit[Index-1] + 1);\r
- }\r
- //\r
- // Retrieve the index into the MTRR to extract the memory type. The range is 0..7\r
- //\r
- TypeIndex = (UINTN)RShiftU64 (Address, mFixedRangeShift[Index]);\r
- \r
- //\r
- // Retrieve and return the memory type for the matching range\r
- //\r
- return mMTRRFixedRange.Fixed[Index].Type[TypeIndex];\r
- }\r
- }\r
- }\r
-\r
- //\r
- // If Address was not found in a Fixed MTRR, then search the Variable MTRRs\r
- //\r
- for (Index = 0, Found = FALSE, VariableType = WriteBack; Index < mMTRRFixedRange.Capabilities.Bits.VCNT; Index++) {\r
- //\r
- // BugBug: __aullshr complier error\r
- //\r
- if ((mMTRRVariableRange[Index].PhysMask.Uint64 & 0x800) == 0x800) { \r
- //if (mMTRRVariableRange[Index].PhysMask.Bits.Valid == 1) {\r
- PhysMask = mMTRRVariableRange[Index].PhysMask.Uint64 & ~0xfff;\r
- MaskBase = PhysMask & (mMTRRVariableRange[Index].PhysBase.Uint64 & ~0xfff);\r
- if (MaskBase == (PhysMask & Address)) {\r
- //\r
- // Check to see how many matches we find\r
- //\r
- Found = TRUE;\r
- if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == Uncached) || (VariableType == Uncached)) {\r
- //\r
- // If any matching region uses UC, the memory region is UC\r
- //\r
- VariableType = Uncached;\r
- } else if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == WriteThrough) || (VariableType == WriteThrough)){\r
- //\r
- // If it's WT and WB then set it to WT. If it's WT and other type it's undefined\r
- //\r
- VariableType = WriteThrough;\r
- } else {\r
- VariableType = mMTRRVariableRange[Index].PhysBase.Bits.Type;\r
- }\r
- }\r
- }\r
- }\r
- \r
- if (Found) {\r
- return VariableType;\r
- }\r
-\r
- //\r
- // Address was not found in the Fixed or Variable MTRRs, so return the default memory type\r
- //\r
- return mMTRRFixedRange.DefaultType.Bits.Type;\r
-}\r
-\r
-\r
-BOOLEAN\r
-CanNotUse2MBPage (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Test to see if a 2MB aligned page has all the same attributes. If a 2MB page\r
- has more than one attibute type it needs to be split into multiple 4K pages.\r
-\r
-Arguments:\r
- BaseAddress - 2MB aligned address to check out\r
-\r
-Returns:\r
- TRUE - This 2MB address range (BaseAddress) can NOT be mapped by a 2MB page\r
- FALSE - This 2MB address range can be mapped by a 2MB page\r
-\r
---*/\r
-{\r
- UINTN Index;\r
- x64_MTRR_MEMORY_TYPE MemoryType;\r
- x64_MTRR_MEMORY_TYPE PreviousMemoryType;\r
- \r
- //\r
- // Address needs to be 2MB aligned\r
- //\r
- ASSERT ((BaseAddress & 0x1fffff) == 0);\r
-\r
- PreviousMemoryType = -1;\r
- for (Index = 0; Index < 512; Index++, BaseAddress += 0x1000) {\r
- MemoryType = EfiGetMTRRMemoryType (BaseAddress);\r
- if ((Index != 0) && (MemoryType != PreviousMemoryType)) {\r
- return TRUE;\r
- }\r
-\r
- PreviousMemoryType = MemoryType;\r
- }\r
-\r
- //\r
- // All the pages had the same type\r
- //\r
- return FALSE;\r
-}\r
-\r
-\r
-\r
-\r
-VOID\r
-Convert2MBPageTo4KPages ( \r
- IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
- IN EFI_PHYSICAL_ADDRESS PageAddress\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Convert a single 2MB page entry to 512 4K page entries. The attributes for \r
- the 4K pages are read from the MTRR registers.\r
-\r
-Arguments:\r
- PageDirectoryEntry2MB - Page directory entry for PageAddress\r
- PageAddress - 2MB algined address of region to convert\r
-\r
-Returns:\r
- None\r
-\r
---*/\r
-{\r
- EFI_PHYSICAL_ADDRESS Address;\r
- x64_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4k;\r
- x64_PAGE_TABLE_ENTRY_4K *PageTableEntry;\r
- UINTN Index1;\r
-\r
- //\r
- // Allocate the page table entry for the 4K pages\r
- //\r
- PageTableEntry = (x64_PAGE_TABLE_ENTRY_4K *) AllocatePages (1);\r
-\r
- ASSERT (PageTableEntry != NULL);\r
-\r
- //\r
- // Convert PageDirectoryEntry2MB into a 4K Page Directory\r
- //\r
- PageDirectoryEntry4k = (x64_PAGE_DIRECTORY_ENTRY_4K *)PageDirectoryEntry2MB;\r
- PageDirectoryEntry2MB->Uint64 = (UINT64)PageTableEntry;\r
- PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
- PageDirectoryEntry2MB->Bits.Present = 1;\r
- \r
- //\r
- // Fill in the 4K page entries with the attributes from the MTRRs\r
- //\r
- for (Index1 = 0, Address = PageAddress; Index1 < 512; Index1++, PageTableEntry++, Address += 0x1000) {\r
- PageTableEntry->Uint64 = (UINT64)Address;\r
- PageTableEntry->Bits.ReadWrite = 1;\r
- PageTableEntry->Bits.Present = 1;\r
- }\r
-}\r
-\r
-\r
-EFI_PHYSICAL_ADDRESS\r
-CreateIdentityMappingPageTables (\r
- IN UINT32 NumberOfProcessorPhysicalAddressBits\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Allocates and fills in the Page Directory and Page Table Entries to\r
- establish a 1:1 Virtual to Physical mapping for physical memory from\r
- 0 to 4GB. Memory above 4GB is not mapped. The MTRRs are used to \r
- determine the cachability of the physical memory regions\r
-\r
-Arguments:\r
-\r
- NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
- Limits the number of page table entries \r
- to the physical address space.\r
-\r
-Returns:\r
- EFI_OUT_OF_RESOURCES There are not enough resources to allocate the Page Tables\r
-\r
- EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
-\r
---*/\r
-{ \r
- EFI_PHYSICAL_ADDRESS PageAddress;\r
- UINTN Index;\r
- UINTN MaxBitsSupported;\r
- UINTN Index1;\r
- UINTN Index2;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMapLevel4Entry;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMap;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageDirectoryPointerEntry;\r
- x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB;\r
-\r
-\r
- //\r
- // Page Table structure 4 level 4K, 3 level 2MB.\r
- //\r
- // PageMapLevel4Entry : bits 47-39\r
- // PageDirectoryPointerEntry : bits 38-30\r
- // Page Table 2MB : PageDirectoryEntry2M : bits 29-21\r
- // Page Table 4K : PageDirectoryEntry4K : bits 29 - 21\r
- // PageTableEntry : bits 20 - 12\r
- //\r
- // Strategy is to map every thing in the processor address space using \r
- // 2MB pages. If more granularity is required the 2MB page will get \r
- // converted to set of 4K pages. \r
- //\r
-\r
- //\r
- // By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.\r
- //\r
- PageMap = PageMapLevel4Entry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
- ASSERT (PageMap != NULL);\r
- PageAddress = 0;\r
-\r
- //\r
- // The number of page-map Level-4 Offset entries is based on the number of \r
- // physical address bits. Less than equal to 38 bits only takes one entry.\r
- // 512 entries represents 48 address bits. \r
- //\r
- if (NumberOfProcessorPhysicalAddressBits <= 38) {\r
- MaxBitsSupported = 1;\r
- } else {\r
- MaxBitsSupported = mPowerOf2[NumberOfProcessorPhysicalAddressBits - 39];\r
- }\r
-\r
- for (Index = 0; Index < MaxBitsSupported; Index++, PageMapLevel4Entry++) {\r
- //\r
- // Each PML4 entry points to a page of Page Directory Pointer entires.\r
- // So lets allocate space for them and fill them in in the Index1 loop.\r
- // \r
- PageDirectoryPointerEntry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
- ASSERT (PageDirectoryPointerEntry != NULL);\r
-\r
- //\r
- // Make a PML4 Entry\r
- //\r
- PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
- PageMapLevel4Entry->Bits.ReadWrite = 1;\r
- PageMapLevel4Entry->Bits.Present = 1;\r
-\r
- for (Index1 = 0; Index1 < 512; Index1++, PageDirectoryPointerEntry++) {\r
- //\r
- // Each Directory Pointer entries points to a page of Page Directory entires.\r
- // So lets allocate space for them and fill them in in the Index2 loop.\r
- // \r
- PageDirectoryEntry2MB = (x64_PAGE_TABLE_ENTRY_2M *) AllocatePages (1);\r
- ASSERT (PageDirectoryEntry2MB != NULL);\r
-\r
- //\r
- // Fill in a Page Directory Pointer Entries\r
- //\r
- PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry2MB;\r
- PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
- PageDirectoryPointerEntry->Bits.Present = 1;\r
-\r
- for (Index2 = 0; Index2 < 512; Index2++, PageDirectoryEntry2MB++, PageAddress += 0x200000) {\r
- //\r
- // Fill in the Page Directory entries\r
- //\r
- PageDirectoryEntry2MB->Uint64 = (UINT64)PageAddress;\r
- PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
- PageDirectoryEntry2MB->Bits.Present = 1;\r
- PageDirectoryEntry2MB->Bits.MustBe1 = 1;\r
-\r
- if (CanNotUse2MBPage (PageAddress)) {\r
- //\r
- // Check to see if all 2MB has the same mapping. If not convert\r
- // to 4K pages by adding the 4th level of page table entries\r
- //\r
- Convert2MBPageTo4KPages (PageDirectoryEntry2MB, PageAddress);\r
- }\r
- }\r
- }\r
- }\r
-\r
- //\r
- // For the PML4 entries we are not using fill in a null entry.\r
- // for now we just copy the first entry.\r
- //\r
- for (; Index < 512; Index++, PageMapLevel4Entry++) {\r
- // EfiCopyMem (PageMapLevel4Entry, PageMap, sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K));\r
- CopyMem (PageMapLevel4Entry,\r
- PageMap,\r
- sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K)\r
- );\r
- }\r
-\r
- return (EFI_PHYSICAL_ADDRESS)PageMap;\r
-}\r
-\r
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