<Filename>atapi.c</Filename>\r
<Filename>ComponentName.c</Filename>\r
<Filename>ComponentName.h</Filename>\r
+ <Filename ToolCode="DUMMY">DriverConfiguration.c</Filename>\r
+ <Filename ToolCode="DUMMY">DriverDiagnostics.h</Filename>\r
</SourceFiles>\r
<PackageDependencies>\r
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
<Filename>pcibus.c</Filename>\r
<Filename>PciIo.c</Filename>\r
<Filename>PciLib.c</Filename>\r
+ <Filename ToolCode="DUMMY">LightPciLib.c</Filename>\r
</SourceFiles>\r
<PackageDependencies>\r
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<!--Copyright (c) 2006, Intel Corporation
-All rights reserved. This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+<!--Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.-->\r
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">\r
<MsaHeader>\r
<Abstract>Component description file for DxeIpl module</Abstract>\r
<Description>The responsibility of this module is to load the DXE Core from a Firmware Volume. This implementation i used to load a 32-bit DXE Core.</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation</Copyright>\r
- <License>All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ <License>All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
</MsaHeader>\r
</LibraryClassDefinitions>\r
<SourceFiles>\r
<Filename>DxeLoad.c</Filename>\r
+ <Filename>DxeIpl.h</Filename>\r
<Filename>DxeIpl.dxs</Filename>\r
<Filename SupArchList="IA32">Ia32/ImageRead.c</Filename>\r
<Filename SupArchList="IA32">Ia32/DxeLoadFunc.c</Filename>\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<!--Copyright (c) 2006, Intel Corporation
-All rights reserved. This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.-->\r
-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">\r
- <MsaHeader>\r
- <ModuleName>DxeIplX64</ModuleName>\r
- <ModuleType>PEIM</ModuleType>\r
- <GuidValue>0c55bdf7-d71d-4962-8fcb-348773e48929</GuidValue>\r
- <Version>1.0</Version>\r
- <Abstract>Component description file for DxeIplX64 module</Abstract>\r
- <Description>The responsibility of this module is to load the DXE Core from a Firmware Volume. This implementation i used to load a 64-bit DXE Core.</Description>\r
- <Copyright>Copyright 2006, Intel Corporation</Copyright>\r
- <License>All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
- <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
- </MsaHeader>\r
- <ModuleDefinitions>\r
- <SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>\r
- <BinaryModule>false</BinaryModule>\r
- <OutputFileBasename>DxeIplX64</OutputFileBasename>\r
- </ModuleDefinitions>\r
- <LibraryClassDefinitions>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>DebugLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>PeimEntryPoint</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>BaseLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>HobLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>PerformanceLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>PeiServicesLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>ReportStatusCodeLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>CacheMaintenanceLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>EdkPeCoffLoaderLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>UefiDecompressLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>TianoDecompressLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>CustomDecompressLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>PeiServicesTablePointerLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>BaseMemoryLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>MemoryAllocationLib</Keyword>\r
- </LibraryClass>\r
- <LibraryClass Usage="ALWAYS_CONSUMED">\r
- <Keyword>EdkPeCoffLoaderX64Lib</Keyword>\r
- </LibraryClass>\r
- </LibraryClassDefinitions>\r
- <SourceFiles>\r
- <Filename>DxeIpl.dxs</Filename>\r
- <Filename>DxeLoadX64.c</Filename>\r
- <Filename SupArchList="IA32">x64/ImageRead.c</Filename>\r
- <Filename SupArchList="IA32">x64/LongMode.asm</Filename>\r
- <Filename SupArchList="IA32">x64/DxeLoadFunc.c</Filename>\r
- <Filename SupArchList="IA32">x64/VirtualMemory.c</Filename>\r
- </SourceFiles>\r
- <PackageDependencies>\r
- <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
- <Package PackageGuid="B6EC423C-21D2-490D-85C6-DD5864EAA674"/>\r
- </PackageDependencies>\r
- <Protocols>\r
- <Protocol Usage="ALWAYS_CONSUMED">\r
- <ProtocolCName>gEfiDecompressProtocolGuid</ProtocolCName>\r
- </Protocol>\r
- <Protocol Usage="ALWAYS_CONSUMED">\r
- <ProtocolCName>gEfiTianoDecompressProtocolGuid</ProtocolCName>\r
- </Protocol>\r
- <Protocol Usage="ALWAYS_CONSUMED">\r
- <ProtocolCName>gEfiCustomizedDecompressProtocolGuid</ProtocolCName>\r
- </Protocol>\r
- </Protocols>\r
- <PPIs>\r
- <Ppi Usage="SOMETIMES_PRODUCED">\r
- <PpiCName>gEfiDxeIplPpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_PRODUCED">\r
- <PpiCName>gEfiPeiFvFileLoaderPpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_PRODUCED">\r
- <PpiCName>gEfiEndOfPeiSignalPpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_CONSUMED">\r
- <PpiCName>gEfiPeiRecoveryModulePpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_CONSUMED">\r
- <PpiCName>gEfiPeiS3ResumePpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_CONSUMED">\r
- <PpiCName>gEfiPeiSectionExtractionPpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="SOMETIMES_CONSUMED">\r
- <PpiCName>gEfiPeiSecurityPpiGuid</PpiCName>\r
- </Ppi>\r
- <Ppi Usage="PRIVATE">\r
- <PpiCName>gPeiInMemoryGuid</PpiCName>\r
- </Ppi>\r
- </PPIs>\r
- <Guids>\r
- <GuidCNames Usage="ALWAYS_CONSUMED">\r
- <GuidCName>gEfiPeiPeCoffLoaderGuid</GuidCName>\r
- </GuidCNames>\r
- </Guids>\r
- <Externs>\r
- <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
- <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
- <Extern>\r
- <ModuleEntryPoint>PeimInitializeDxeIpl</ModuleEntryPoint>\r
- </Extern>\r
- </Externs>\r
-</ModuleSurfaceArea>
\ No newline at end of file
+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- DxeLoad.c\r
-\r
-Abstract:\r
-\r
- Last PEIM.\r
- Responsibility of this module is to load the DXE Core from a Firmware Volume.\r
-\r
---*/\r
-\r
-#include <DxeIpl.h>\r
-\r
-#pragma warning( disable : 4305 )\r
-\r
-BOOLEAN gInMemory = FALSE;\r
-\r
-//\r
-// GUID for EM64T\r
-//\r
-#define EFI_PPI_NEEDED_BY_DXE \\r
- { \\r
- 0x4d37da42, 0x3a0c, 0x4eda, 0xb9, 0xeb, 0xbc, 0x0e, 0x1d, 0xb4, 0x71, 0x3b \\r
- }\r
-EFI_GUID mPpiNeededByDxeGuid = EFI_PPI_NEEDED_BY_DXE;\r
-\r
-//\r
-// Module Globals used in the DXE to PEI handoff\r
-// These must be module globals, so the stack can be switched\r
-//\r
-static EFI_DXE_IPL_PPI mDxeIplPpi = {\r
- DxeLoadCore\r
-};\r
-\r
-static EFI_PEI_FV_FILE_LOADER_PPI mLoadFilePpi = {\r
- DxeIplLoadFile\r
-};\r
-\r
-static EFI_PEI_PPI_DESCRIPTOR mPpiLoadFile = {\r
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
- &gEfiPeiFvFileLoaderPpiGuid,\r
- &mLoadFilePpi\r
-};\r
-\r
-static EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
- &gEfiDxeIplPpiGuid,\r
- &mDxeIplPpi\r
-};\r
-\r
-static EFI_PEI_PPI_DESCRIPTOR mPpiPeiInMemory = {\r
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
- &gPeiInMemoryGuid,\r
- NULL\r
-};\r
-\r
-static EFI_PEI_PPI_DESCRIPTOR mPpiSignal = {\r
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
- &gEfiEndOfPeiSignalPpiGuid,\r
- NULL\r
-};\r
-\r
-DECOMPRESS_LIBRARY gEfiDecompress = {\r
- UefiDecompressGetInfo,\r
- UefiDecompress\r
-};\r
-\r
-DECOMPRESS_LIBRARY gTianoDecompress = {\r
- TianoDecompressGetInfo,\r
- TianoDecompress\r
-};\r
-\r
-DECOMPRESS_LIBRARY gCustomDecompress = {\r
- CustomDecompressGetInfo,\r
- CustomDecompress\r
-};\r
-\r
-STATIC\r
-UINTN\r
-GetOccupiedSize (\r
- IN UINTN ActualSize,\r
- IN UINTN Alignment\r
- )\r
-{\r
- UINTN OccupiedSize;\r
-\r
- OccupiedSize = ActualSize;\r
- while ((OccupiedSize & (Alignment - 1)) != 0) {\r
- OccupiedSize++;\r
- }\r
-\r
- return OccupiedSize;\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PeimInitializeDxeIpl (\r
- IN EFI_FFS_FILE_HEADER *FfsHeader,\r
- IN EFI_PEI_SERVICES **PeiServices\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Initializes the Dxe Ipl PPI\r
-\r
-Arguments:\r
-\r
- FfsHeader - Pointer to FFS file header\r
- PeiServices - General purpose services available to every PEIM.\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
- EFI_BOOT_MODE BootMode;\r
-\r
- Status = PeiServicesGetBootMode (&BootMode);\r
-\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = PeiServicesLocatePpi (\r
- &gPeiInMemoryGuid,\r
- 0,\r
- NULL,\r
- NULL\r
- );\r
-\r
- if (EFI_ERROR (Status) && (BootMode != BOOT_ON_S3_RESUME)) { \r
- //\r
- // The DxeIpl has not yet been shadowed\r
- //\r
- PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
-\r
- //\r
- // Shadow DxeIpl and then re-run its entry point\r
- //\r
- Status = ShadowDxeIpl (FfsHeader, PeiEfiPeiPeCoffLoader);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- } else {\r
- if (BootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // The DxeIpl has been shadowed\r
- //\r
- gInMemory = TRUE;\r
-\r
- //\r
- // Install LoadFile PPI\r
- //\r
- Status = PeiServicesInstallPpi (&mPpiLoadFile);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
- //\r
- // Install DxeIpl PPI\r
- //\r
- PeiServicesInstallPpi (&mPpiList);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-DxeLoadCore (\r
- IN EFI_DXE_IPL_PPI *This,\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_HOB_POINTERS HobList\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Main entry point to last PEIM\r
-\r
-Arguments:\r
-\r
- This - Entry point for DXE IPL PPI\r
- PeiServices - General purpose services available to every PEIM.\r
- HobList - Address to the Pei HOB list\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - DEX core was successfully loaded.\r
- EFI_OUT_OF_RESOURCES - There are not enough resources to load DXE core.\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS TopOfStack;\r
- EFI_PHYSICAL_ADDRESS BaseOfStack;\r
- EFI_PHYSICAL_ADDRESS BspStore;\r
- EFI_GUID DxeCoreFileName;\r
- VOID *DxeCorePe32Data;\r
- EFI_PHYSICAL_ADDRESS DxeCoreAddress;\r
- UINT64 DxeCoreSize;\r
- EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;\r
- EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
- EFI_BOOT_MODE BootMode;\r
- EFI_PEI_RECOVERY_MODULE_PPI *PeiRecovery;\r
- EFI_PEI_S3_RESUME_PPI *S3Resume;\r
- EFI_PHYSICAL_ADDRESS PageTables;\r
- \r
- TopOfStack = 0;\r
- BaseOfStack = 0;\r
- BspStore = 0;\r
- Status = EFI_SUCCESS;\r
-\r
- //\r
- // if in S3 Resume, restore configure\r
- //\r
- Status = PeiServicesGetBootMode (&BootMode);\r
-\r
- if (!EFI_ERROR (Status) && (BootMode == BOOT_ON_S3_RESUME)) {\r
- Status = PeiServicesLocatePpi (\r
- &gEfiPeiS3ResumePpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&S3Resume\r
- );\r
-\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = S3Resume->S3RestoreConfig (PeiServices);\r
-\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-\r
- Status = EFI_SUCCESS;\r
-\r
- //\r
- // Install the PEI Protocols that are shared between PEI and DXE\r
- //\r
-#ifdef EFI_NT_EMULATOR\r
- PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
- ASSERT (PeiEfiPeiPeCoffLoader != NULL);\r
-#else\r
- PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderX64Protocol ();\r
-#endif \r
-\r
-#if 0\r
- Status = InstallEfiPeiPeCoffLoader64 (PeiServices, &PeiEfiPeiPeCoffLoader, NULL);\r
- ASSERT_EFI_ERROR (Status);\r
-#endif\r
- //\r
- // Allocate 128KB for the Stack\r
- //\r
- PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r
- ASSERT (BaseOfStack != 0);\r
-\r
- //\r
- // Compute the top of the stack we were allocated. Pre-allocate a 32 bytes\r
- // for safety (PpisNeededByDxe and DxeCore).\r
- //\r
- TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
-\r
- //\r
- // Add architecture-specifc HOBs (including the BspStore HOB)\r
- //\r
- Status = CreateArchSpecificHobs (&BspStore);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // See if we are in crisis recovery\r
- //\r
- Status = PeiServicesGetBootMode (&BootMode);\r
- if (!EFI_ERROR (Status) && (BootMode == BOOT_IN_RECOVERY_MODE)) {\r
- Status = PeiServicesLocatePpi (\r
- &gEfiPeiRecoveryModulePpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&PeiRecovery\r
- );\r
-\r
- ASSERT_EFI_ERROR (Status);\r
- Status = PeiRecovery->LoadRecoveryCapsule (PeiServices, PeiRecovery);\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-\r
- //\r
- // Find the DXE Core in a Firmware Volume\r
- //\r
- Status = PeiFindFile (\r
- EFI_FV_FILETYPE_DXE_CORE,\r
- EFI_SECTION_PE32,\r
- &DxeCoreFileName,\r
- &DxeCorePe32Data\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Transfer control to the DXE Core\r
- // The handoff state is simply a pointer to the HOB list\r
- //\r
- // PEI_PERF_END (PeiServices, L"DxeIpl", NULL, 0);\r
-\r
- Status = PeiServicesInstallPpi (&mPpiSignal);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA \\r
- // memory, it may be corrupted when copying FV to high-end memory \r
- LoadGo64Gdt();\r
-\r
- //\r
- // Limit to 36 bits of addressing for debug. Should get it from CPU\r
- //\r
- PageTables = CreateIdentityMappingPageTables (36);\r
-\r
-\r
- //\r
- // Load the DXE Core from a Firmware Volume\r
- //\r
- Status = PeiLoadx64File (\r
- PeiEfiPeiPeCoffLoader,\r
- DxeCorePe32Data,\r
- EfiBootServicesData,\r
- &DxeCoreAddress,\r
- &DxeCoreSize,\r
- &DxeCoreEntryPoint\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- //\r
- // Add HOB for the DXE Core\r
- //\r
- BuildModuleHob (\r
- &DxeCoreFileName,\r
- DxeCoreAddress,\r
- DxeCoreSize,\r
- DxeCoreEntryPoint\r
- );\r
-\r
- //\r
- // Report Status Code EFI_SW_PEI_PC_HANDOFF_TO_NEXT\r
- //\r
- REPORT_STATUS_CODE (\r
- EFI_PROGRESS_CODE,\r
- EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT\r
- );\r
-\r
- DEBUG ((EFI_D_INFO, "DXE Core Entry\n"));\r
- //\r
- // Go to Long Mode. Interrupts will not get turned on until the CPU AP is loaded.\r
- // Call x64 drivers passing in single argument, a pointer to the HOBs.\r
- //\r
- ActivateLongMode (\r
- PageTables, \r
- (EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw), \r
- TopOfStack,\r
- 0x00000000,\r
- DxeCoreEntryPoint\r
- );\r
-\r
- //\r
- // If we get here, then the DXE Core returned. This is an error\r
- //\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_OUT_OF_RESOURCES;\r
-}\r
-\r
-EFI_STATUS\r
-PeiFindFile (\r
- IN UINT8 Type,\r
- IN UINT16 SectionType,\r
- OUT EFI_GUID *FileName,\r
- OUT VOID **Pe32Data\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Finds a PE/COFF of a specific Type and SectionType in the Firmware Volumes\r
- described in the HOB list. Able to search in a compression set in a FFS file.\r
- But only one level of compression is supported, that is, not able to search\r
- in a compression set that is within another compression set.\r
-\r
-Arguments:\r
-\r
- Type - The Type of file to retrieve\r
-\r
- SectionType - The type of section to retrieve from a file\r
-\r
- FileName - The name of the file found in the Firmware Volume\r
-\r
- Pe32Data - Pointer to the beginning of the PE/COFF file found in the Firmware Volume\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - The file was found, and the name is returned in FileName, and a pointer to\r
- the PE/COFF image is returned in Pe32Data\r
-\r
- EFI_NOT_FOUND - The file was not found in the Firmware Volumes present in the HOB List\r
-\r
---*/\r
-{\r
- EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
- EFI_FFS_FILE_HEADER *FfsFileHeader;\r
- VOID *SectionData;\r
- EFI_STATUS Status;\r
- EFI_PEI_HOB_POINTERS Hob;\r
-\r
-\r
- FwVolHeader = NULL;\r
- FfsFileHeader = NULL;\r
- SectionData = NULL;\r
-\r
- //\r
- // Foreach Firmware Volume, look for a specified type\r
- // of file and break out when one is found\r
- //\r
- Hob.Raw = GetHobList ();\r
- while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_FV, Hob.Raw)) != NULL) {\r
- FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) (Hob.FirmwareVolume->BaseAddress);\r
- Status = PeiServicesFfsFindNextFile (\r
- Type,\r
- FwVolHeader,\r
- &FfsFileHeader\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- Status = PeiProcessFile (\r
- SectionType,\r
- &FfsFileHeader,\r
- Pe32Data\r
- );\r
- CopyMem (FileName, &FfsFileHeader->Name, sizeof (EFI_GUID));\r
- return Status;\r
- }\r
- Hob.Raw = GET_NEXT_HOB (Hob);\r
- }\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
-EFI_STATUS\r
-PeiLoadx64File (\r
- IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader,\r
- IN VOID *Pe32Data,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
- OUT UINT64 *ImageSize,\r
- OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Loads and relocates a PE/COFF image into memory.\r
-\r
-Arguments:\r
-\r
- PeiEfiPeiPeCoffLoader - Pointer to a PE COFF loader protocol\r
-\r
- Pe32Data - The base address of the PE/COFF file that is to be loaded and relocated\r
-\r
- ImageAddress - The base address of the relocated PE/COFF image\r
-\r
- ImageSize - The size of the relocated PE/COFF image\r
-\r
- EntryPoint - The entry point of the relocated PE/COFF image\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - The file was loaded and relocated\r
- EFI_OUT_OF_RESOURCES - There was not enough memory to load and relocate the PE/COFF file\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
- EFI_PHYSICAL_ADDRESS MemoryBuffer;\r
-\r
- ZeroMem (&ImageContext, sizeof (ImageContext));\r
- ImageContext.Handle = Pe32Data;\r
- Status = GetImageReadFunction (&ImageContext);\r
-\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = PeiEfiPeiPeCoffLoader->GetImageInfo (PeiEfiPeiPeCoffLoader, &ImageContext);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Allocate Memory for the image\r
- //\r
- //\r
- // Allocate Memory for the image\r
- //\r
- PeiServicesAllocatePages (MemoryType, EFI_SIZE_TO_PAGES ((UINT32) ImageContext.ImageSize), &MemoryBuffer);\r
- ImageContext.ImageAddress = MemoryBuffer;\r
- ASSERT (ImageContext.ImageAddress != 0);\r
-\r
- //\r
- // Load the image to our new buffer\r
- //\r
-\r
- Status = PeiEfiPeiPeCoffLoader->LoadImage (PeiEfiPeiPeCoffLoader, &ImageContext);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- \r
- //\r
- // Relocate the image in our new buffer\r
- //\r
- Status = PeiEfiPeiPeCoffLoader->RelocateImage (PeiEfiPeiPeCoffLoader, &ImageContext);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Flush the instruction cache so the image data is written before we execute it\r
- //\r
- InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);\r
-\r
- *ImageAddress = ImageContext.ImageAddress;\r
- *ImageSize = ImageContext.ImageSize;\r
- *EntryPoint = ImageContext.EntryPoint;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-ShadowDxeIpl (\r
- IN EFI_FFS_FILE_HEADER *DxeIplFileHeader,\r
- IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Shadow the DXE IPL to a different memory location. This occurs after permanent\r
- memory has been discovered.\r
-\r
-Arguments:\r
-\r
- DxeIplFileHeader - Pointer to the FFS file header of the DXE IPL driver\r
-\r
- PeiEfiPeiPeCoffLoader - Pointer to a PE COFF loader protocol\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - DXE IPL was successfully shadowed to a different memory location.\r
-\r
- EFI_ ERROR - The shadow was unsuccessful.\r
-\r
-\r
---*/\r
-{\r
- UINTN SectionLength;\r
- UINTN OccupiedSectionLength;\r
- EFI_PHYSICAL_ADDRESS DxeIplAddress;\r
- UINT64 DxeIplSize;\r
- EFI_PHYSICAL_ADDRESS DxeIplEntryPoint;\r
- EFI_STATUS Status;\r
- EFI_COMMON_SECTION_HEADER *Section;\r
-\r
- Section = (EFI_COMMON_SECTION_HEADER *) (DxeIplFileHeader + 1);\r
-\r
- while ((Section->Type != EFI_SECTION_PE32) && (Section->Type != EFI_SECTION_TE)) {\r
- SectionLength = *(UINT32 *) (Section->Size) & 0x00ffffff;\r
- OccupiedSectionLength = GetOccupiedSize (SectionLength, 4);\r
- Section = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) Section + OccupiedSectionLength);\r
- }\r
- \r
- //\r
- // Relocate DxeIpl into memory by using loadfile service\r
- //\r
- Status = PeiLoadx64File (\r
- PeiEfiPeiPeCoffLoader,\r
- (VOID *) (Section + 1),\r
- EfiBootServicesData,\r
- &DxeIplAddress,\r
- &DxeIplSize,\r
- &DxeIplEntryPoint\r
- );\r
- \r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // Install PeiInMemory to indicate the Dxeipl is shadowed\r
- //\r
- Status = PeiServicesInstallPpi (&mPpiPeiInMemory);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- Status = ((EFI_PEIM_ENTRY_POINT) (UINTN) DxeIplEntryPoint) (DxeIplFileHeader, GetPeiServicesTablePointer());\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-DxeIplLoadFile (\r
- IN EFI_PEI_FV_FILE_LOADER_PPI *This,\r
- IN EFI_FFS_FILE_HEADER *FfsHeader,\r
- OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
- OUT UINT64 *ImageSize,\r
- OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Given a pointer to an FFS file containing a PE32 image, get the\r
- information on the PE32 image, and then "load" it so that it\r
- can be executed.\r
-\r
-Arguments:\r
-\r
- This - pointer to our file loader protocol\r
- FfsHeader - pointer to the FFS file header of the FFS file that\r
- contains the PE32 image we want to load\r
- ImageAddress - returned address where the PE32 image is loaded\r
- ImageSize - returned size of the loaded PE32 image\r
- EntryPoint - entry point to the loaded PE32 image\r
-\r
-Returns:\r
- \r
- EFI_SUCCESS - The FFS file was successfully loaded.\r
- EFI_ERROR - Unable to load the FFS file.\r
-\r
---*/\r
-{\r
- EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
- EFI_STATUS Status;\r
- VOID *Pe32Data;\r
-\r
- Pe32Data = NULL;\r
- PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
-\r
- //\r
- // Preprocess the FFS file to get a pointer to the PE32 information\r
- // in the enclosed PE32 image.\r
- //\r
- Status = PeiProcessFile (\r
- EFI_SECTION_PE32,\r
- &FfsHeader,\r
- &Pe32Data\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Load the PE image from the FFS file\r
- //\r
- Status = PeiLoadx64File (\r
- PeiEfiPeiPeCoffLoader,\r
- Pe32Data,\r
- EfiBootServicesData,\r
- ImageAddress,\r
- ImageSize,\r
- EntryPoint\r
- );\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-PeiProcessFile (\r
- IN UINT16 SectionType,\r
- IN OUT EFI_FFS_FILE_HEADER **RealFfsFileHeader,\r
- OUT VOID **Pe32Data\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
- SectionType - The type of section in the FFS file to process.\r
-\r
- FfsFileHeader - Pointer to the FFS file to process, looking for the\r
- specified SectionType\r
-\r
- Pe32Data - returned pointer to the start of the PE32 image found\r
- in the FFS file.\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - found the PE32 section in the FFS file\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- VOID *SectionData;\r
- DECOMPRESS_LIBRARY *DecompressLibrary;\r
- UINT8 *DstBuffer;\r
- UINT8 *ScratchBuffer;\r
- UINT32 DstBufferSize;\r
- UINT32 ScratchBufferSize;\r
- EFI_COMMON_SECTION_HEADER *CmpSection;\r
- UINTN CmpSectionLength;\r
- UINTN OccupiedCmpSectionLength;\r
- VOID *CmpFileData;\r
- UINTN CmpFileSize;\r
- EFI_COMMON_SECTION_HEADER *Section;\r
- UINTN SectionLength;\r
- UINTN OccupiedSectionLength;\r
- UINT64 FileSize;\r
- EFI_GUID_DEFINED_SECTION *GuidedSectionHeader;\r
- UINT32 AuthenticationStatus;\r
- EFI_PEI_SECTION_EXTRACTION_PPI *SectionExtract;\r
- UINT32 BufferSize;\r
- UINT8 *Buffer;\r
- EFI_PEI_SECURITY_PPI *Security;\r
- BOOLEAN StartCrisisRecovery;\r
- EFI_GUID TempGuid;\r
- EFI_FIRMWARE_VOLUME_HEADER *FvHeader;\r
- EFI_COMPRESSION_SECTION *CompressionSection;\r
- EFI_FFS_FILE_HEADER *FfsFileHeader;\r
- \r
- FfsFileHeader = *RealFfsFileHeader;\r
-\r
- Status = PeiServicesFfsFindSectionData (\r
- EFI_SECTION_COMPRESSION,\r
- FfsFileHeader,\r
- &SectionData\r
- );\r
-\r
- //\r
- // Upon finding a DXE Core file, see if there is first a compression section\r
- //\r
- if (!EFI_ERROR (Status)) {\r
- //\r
- // Yes, there is a compression section, so extract the contents\r
- // Decompress the image here\r
- //\r
- Section = (EFI_COMMON_SECTION_HEADER *) (UINTN) (VOID *) ((UINT8 *) (FfsFileHeader) + (UINTN) sizeof (EFI_FFS_FILE_HEADER));\r
-\r
- do {\r
- SectionLength = *(UINT32 *) (Section->Size) & 0x00ffffff;\r
- OccupiedSectionLength = GetOccupiedSize (SectionLength, 4);\r
-\r
- //\r
- // Was the DXE Core file encapsulated in a GUID'd section?\r
- //\r
- if (Section->Type == EFI_SECTION_GUID_DEFINED) {\r
- //\r
- // Locate the GUID'd Section Extractor\r
- //\r
- GuidedSectionHeader = (VOID *) (Section + 1);\r
-\r
- //\r
- // This following code constitutes the addition of the security model\r
- // to the DXE IPL.\r
- //\r
- //\r
- // Set a default authenticatino state\r
- //\r
- AuthenticationStatus = 0;\r
-\r
- Status = PeiServicesLocatePpi (\r
- &gEfiPeiSectionExtractionPpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&SectionExtract\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Verify Authentication State\r
- //\r
- CopyMem (&TempGuid, Section + 1, sizeof (EFI_GUID));\r
-\r
- Status = SectionExtract->PeiGetSection (\r
- GetPeiServicesTablePointer(),\r
- SectionExtract,\r
- (EFI_SECTION_TYPE *) &SectionType,\r
- &TempGuid,\r
- 0,\r
- (VOID **) &Buffer,\r
- &BufferSize,\r
- &AuthenticationStatus\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // If not ask the Security PPI, if exists, for disposition\r
- //\r
- //\r
- Status = PeiServicesLocatePpi (\r
- &gEfiPeiSecurityPpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&Security\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- Status = Security->AuthenticationState (\r
- GetPeiServicesTablePointer(),\r
- (struct _EFI_PEI_SECURITY_PPI *) Security,\r
- AuthenticationStatus,\r
- FfsFileHeader,\r
- &StartCrisisRecovery\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // If there is a security violation, report to caller and have\r
- // the upper-level logic possible engender a crisis recovery\r
- //\r
- if (StartCrisisRecovery) {\r
- return EFI_SECURITY_VIOLATION;\r
- }\r
- }\r
-\r
- if (Section->Type == EFI_SECTION_PE32) {\r
- //\r
- // This is what we want\r
- //\r
- *Pe32Data = (VOID *) (Section + 1);\r
- return EFI_SUCCESS;\r
- } else if (Section->Type == EFI_SECTION_COMPRESSION) {\r
- //\r
- // This is a compression set, expand it\r
- //\r
- CompressionSection = (EFI_COMPRESSION_SECTION *) Section;\r
-\r
- switch (CompressionSection->CompressionType) {\r
- case EFI_STANDARD_COMPRESSION:\r
- DecompressLibrary = &gTianoDecompress;\r
- break;\r
-\r
- case EFI_CUSTOMIZED_COMPRESSION:\r
- //\r
- // Load user customized compression protocol.\r
- //\r
- DecompressLibrary = &gCustomDecompress;\r
- break;\r
-\r
- case EFI_NOT_COMPRESSED:\r
- default:\r
- //\r
- // Need to support not compressed file\r
- //\r
- ASSERT_EFI_ERROR (Status);\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- Status = DecompressLibrary->GetInfo (\r
- (UINT8 *) ((EFI_COMPRESSION_SECTION *) Section + 1),\r
- (UINT32) SectionLength - sizeof (EFI_COMPRESSION_SECTION),\r
- &DstBufferSize,\r
- &ScratchBufferSize\r
- );\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // GetInfo failed\r
- //\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Allocate scratch buffer\r
- //\r
- ScratchBuffer = AllocatePages (EFI_SIZE_TO_PAGES (ScratchBufferSize));\r
- if (ScratchBuffer == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- //\r
- // Allocate destination buffer\r
- //\r
- DstBuffer = AllocatePages (EFI_SIZE_TO_PAGES (DstBufferSize));\r
- if (DstBuffer == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- //\r
- // Call decompress function\r
- //\r
- Status = DecompressLibrary->Decompress (\r
- (CHAR8 *) ((EFI_COMPRESSION_SECTION *) Section + 1),\r
- DstBuffer,\r
- ScratchBuffer\r
- );\r
-\r
- CmpSection = (EFI_COMMON_SECTION_HEADER *) DstBuffer;\r
- if (CmpSection->Type == EFI_SECTION_RAW) {\r
- //\r
- // Skip the section header and\r
- // adjust the pointer alignment to 16\r
- //\r
- FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (DstBuffer + 16);\r
-\r
- if (FvHeader->Signature == EFI_FVH_SIGNATURE) {\r
- FfsFileHeader = NULL;\r
- BuildFvHob ((EFI_PHYSICAL_ADDRESS) (UINTN) FvHeader, FvHeader->FvLength);\r
- Status = PeiServicesFfsFindNextFile (\r
- EFI_FV_FILETYPE_DXE_CORE,\r
- FvHeader,\r
- &FfsFileHeader\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Reture the FfsHeader that contain Pe32Data.\r
- //\r
- *RealFfsFileHeader = FfsFileHeader;\r
- return PeiProcessFile (SectionType, RealFfsFileHeader, Pe32Data);\r
- }\r
- }\r
- //\r
- // Decompress successfully.\r
- // Loop the decompressed data searching for expected section.\r
- //\r
- CmpFileData = (VOID *) DstBuffer;\r
- CmpFileSize = DstBufferSize;\r
- do {\r
- CmpSectionLength = *(UINT32 *) (CmpSection->Size) & 0x00ffffff;\r
- if (CmpSection->Type == EFI_SECTION_PE32) {\r
- //\r
- // This is what we want\r
- //\r
- *Pe32Data = (VOID *) (CmpSection + 1);\r
- return EFI_SUCCESS;\r
- }\r
-\r
- OccupiedCmpSectionLength = GetOccupiedSize (CmpSectionLength, 4);\r
- CmpSection = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) CmpSection + OccupiedCmpSectionLength);\r
- } while (CmpSection->Type != 0 && (UINTN) ((UINT8 *) CmpSection - (UINT8 *) CmpFileData) < CmpFileSize);\r
- }\r
-\r
- Section = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) Section + OccupiedSectionLength);\r
- FileSize = FfsFileHeader->Size[0] & 0xFF;\r
- FileSize += (FfsFileHeader->Size[1] << 8) & 0xFF00;\r
- FileSize += (FfsFileHeader->Size[2] << 16) & 0xFF0000;\r
- FileSize &= 0x00FFFFFF;\r
- } while (Section->Type != 0 && (UINTN) ((UINT8 *) Section - (UINT8 *) FfsFileHeader) < FileSize);\r
-\r
- //\r
- // End of the decompression activity\r
- //\r
- } else {\r
-\r
- Status = PeiServicesFfsFindSectionData (\r
- EFI_SECTION_PE32,\r
- FfsFileHeader,\r
- &SectionData\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- Status = PeiServicesFfsFindSectionData (\r
- EFI_SECTION_TE,\r
- FfsFileHeader,\r
- &SectionData\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
- }\r
-\r
- *Pe32Data = SectionData;\r
-\r
- return EFI_SUCCESS;\r
-}
\ No newline at end of file
+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- DxeLoadFunc.c\r
-\r
-Abstract:\r
-\r
- Ia32-specifc functionality for DxeLoad X64 Lakeport.\r
-\r
---*/\r
-\r
-#include <DxeIpl.h>\r
-\r
-EFI_STATUS\r
-CreateArchSpecificHobs (\r
- OUT EFI_PHYSICAL_ADDRESS *BspStore\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Creates architecture-specific HOBs.\r
-\r
- Note: New parameters should NOT be added for any HOBs that are added to this\r
- function. BspStore is a special case because it is required for the\r
- call to SwitchStacks() in DxeLoad().\r
-\r
-Arguments:\r
-\r
- PeiServices - General purpose services available to every PEIM.\r
- BspStore - The address of the BSP Store for those architectures that need\r
- it. Otherwise 0.\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - The HOBs were created successfully.\r
-\r
---*/\r
-{\r
- *BspStore = 0;\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- ImageRead.c\r
-\r
-Abstract:\r
-\r
---*/\r
-\r
-#include <DxeIpl.h>\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PeiImageRead (\r
- IN VOID *FileHandle,\r
- IN UINTN FileOffset,\r
- IN OUT UINTN *ReadSize,\r
- OUT VOID *Buffer\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Support routine for the PE/COFF Loader that reads a buffer from a PE/COFF file\r
-\r
-Arguments:\r
-\r
- FileHandle - The handle to the PE/COFF file\r
-\r
- FileOffset - The offset, in bytes, into the file to read\r
-\r
- ReadSize - The number of bytes to read from the file starting at FileOffset\r
-\r
- Buffer - A pointer to the buffer to read the data into.\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - ReadSize bytes of data were read into Buffer from the PE/COFF file starting at FileOffset\r
-\r
---*/\r
-{\r
- CHAR8 *Destination8;\r
- CHAR8 *Source8;\r
- UINTN Length;\r
-\r
- Destination8 = Buffer;\r
- Source8 = (CHAR8 *) ((UINTN) FileHandle + FileOffset);\r
- Length = *ReadSize;\r
- while (Length--) {\r
- *(Destination8++) = *(Source8++);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-GetImageReadFunction (\r
- IN PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Support routine to return the PE32 Image Reader.\r
- If the PeiImageRead() function is less than a page\r
- in legnth. If the function is more than a page the DXE IPL will crash!!!!\r
-\r
-Arguments:\r
- ImageContext - The context of the image being loaded\r
-\r
-Returns:\r
-\r
- EFI_SUCCESS - If Image function location is found\r
-\r
---*/\r
-{\r
- VOID *MemoryBuffer;\r
-\r
- if (gInMemory) {\r
- ImageContext->ImageRead = PeiImageRead;\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // BugBug; This code assumes PeiImageRead() is less than a page in size!\r
- // Allocate a page so we can shaddow the read function from FLASH into \r
- // memory to increase performance. \r
- //\r
- \r
- MemoryBuffer = AllocateCopyPool (0x400, (VOID *)(UINTN) PeiImageRead);\r
- ASSERT (MemoryBuffer != NULL);\r
-\r
- ImageContext->ImageRead = (PE_COFF_LOADER_READ_FILE) (UINTN) MemoryBuffer;\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
- TITLE LongMode.asm: Assembly code for the entering long mode
-
-;------------------------------------------------------------------------------
-;*
-;* Copyright (c) 2006, Intel Corporation
-;* All rights reserved. This program and the accompanying materials
-;* are licensed and made available under the terms and conditions of the BSD License
-;* which accompanies this distribution. The full text of the license may be found at
-;* http://opensource.org/licenses/bsd-license.php
-;*
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;*
-;* LongMode.asm
-;*
-;* Abstract:
-;*
-;* Transition from 32-bit protected mode EFI environment into x64
-;* 64-bit bit long mode.
-;*
-;------------------------------------------------------------------------------
-
-.686p
-.model flat
-
-;
-; Create the exception handler code in IA32 C code
-;
-
-.code
-.stack
-.MMX
-.XMM
-
-_LoadGo64Gdt PROC Near Public
- push ebp ; C prolog
- push edi
- mov ebp, esp
- ;
- ; Disable interrupts
- ;
- cli
- ;
- ; Reload the selectors
- ; Note:
- ; Make the Selectors 64-bit ready
- ;
- mov edi, OFFSET gdtr ; Load GDT register
- mov ax,cs ; Get the selector data from our code image
- mov es,ax
- lgdt FWORD PTR es:[edi] ; and update the GDTR
-
- db 067h
- db 0eah ; Far Jump Offset:Selector to reload CS
- dd OFFSET DataSelectorRld; Offset is ensuing instruction boundary
- dw LINEAR_CODE_SEL ; Selector is our code selector, 10h
-DataSelectorRld::
- mov ax, SYS_DATA_SEL ; Update the Base for the new selectors, too
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- pop edi
- pop ebp
- ret
-_LoadGo64Gdt endp
-
-
-; VOID
-; ActivateLongMode (
-; IN EFI_PHYSICAL_ADDRESS PageTables,
-; IN EFI_PHYSICAL_ADDRESS HobStart,
-; IN EFI_PHYSICAL_ADDRESS Stack,
-; IN EFI_PHYSICAL_ADDRESS PpisNeededByDxeIplEntryPoint,
-; IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint
-; )
-;
-; Input: [ebp][0h] = Original ebp
-; [ebp][4h] = Return address
-; [ebp][8h] = PageTables
-; [ebp][10h] = HobStart
-; [ebp][18h] = Stack
-; [ebp][20h] = CodeEntryPoint1 <--- Call this first (for each call, pass HOB pointer)
-; [ebp][28h] = CodeEntryPoint2 <--- Call this second
-;
-;
-_ActivateLongMode PROC Near Public
- push ebp ; C prolog
- mov ebp, esp
-
- ;
- ; Use CPUID to determine if the processor supports long mode.
- ;
- mov eax, 80000000h ; Extended-function code 8000000h.
- cpuid ; Is largest extended function
- cmp eax, 80000000h ; any function > 80000000h?
- jbe no_long_mode ; If not, no long mode.
- mov eax, 80000001h ; Extended-function code 8000001h.
- cpuid ; Now EDX = extended-features flags.
- bt edx, 29 ; Test if long mode is supported.
- jnc no_long_mode ; Exit if not supported.
-
- ;
- ; Enable the 64-bit page-translation-table entries by
- ; setting CR4.PAE=1 (this is _required_ before activating
- ; long mode). Paging is not enabled until after long mode
- ; is enabled.
- ;
- mov eax, cr4
- bts eax, 5
- mov cr4, eax
-
- ;
- ; Get the long-mode page tables, and initialize the
- ; 64-bit CR3 (page-table base address) to point to the base
- ; of the PML4 page table. The PML4 page table must be located
- ; below 4 Gbytes because only 32 bits of CR3 are loaded when
- ; the processor is not in 64-bit mode.
- ;
- mov eax, [ebp+8h] ; Get Page Tables
- mov cr3, eax ; Initialize CR3 with PML4 base.
-
- ;
- ; Enable long mode (set EFER.LME=1).
- ;
- mov ecx, 0c0000080h ; EFER MSR number.
- rdmsr ; Read EFER.
- bts eax, 8 ; Set LME=1.
- wrmsr ; Write EFER.
-
- ;
- ; Enable paging to activate long mode (set CR0.PG=1)
- ;
-
-
- mov eax, cr0 ; Read CR0.
- bts eax, 31 ; Set PG=1.
- mov cr0, eax ; Write CR0.
- jmp go_to_long_mode
-go_to_long_mode:
-
- ;
- ; This is the next instruction after enabling paging. Jump to long mode
- ;
- db 067h
- db 0eah ; Far Jump Offset:Selector to reload CS
- dd OFFSET in_long_mode; Offset is ensuing instruction boundary
- dw SYS_CODE64_SEL ; Selector is our code selector, 10h
-in_long_mode::
- mov ax, SYS_DATA64_SEL
- mov es, ax
- mov ss, ax
- mov ds, ax
-;; jmp $
-
-
- ;
- ; We're in long mode, so marshall the arguments to call the
- ; passed in function pointers
- ; Recall
- ; [ebp][10h] = HobStart
- ; [ebp][18h] = Stack
- ; [ebp][20h] = PpisNeededByDxeIplEntryPoint <--- Call this first (for each call, pass HOB pointer)
- ; [ebp][28h] = DxeCoreEntryPoint <--- Call this second
- ;
- db 48h
- mov ebx, [ebp+18h] ; Setup the stack
- db 48h
- mov esp, ebx ; On a new stack now
-
-
-;; 00000905 FF D0 call rax
-
- db 48h
- mov ecx, [ebp+10h] ; Pass Hob Start in RCX
- db 48h
- mov eax, [ebp+28h] ; Get the function pointer for
- ; DxeCoreEntryPoint into EAX
-
-;; 00000905 FF D0 call rax
- db 0ffh
- db 0d0h
-
- ;
- ; WE SHOULD NEVER GET HERE!!!!!!!!!!!!!
- ;
-no_long_mode:
- jmp no_long_mode
-_ActivateLongMode endp
-
- align 16
-
-gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit
- dd OFFSET GDT_BASE ; (GDT base gets set above)
-
-;-----------------------------------------------------------------------------;
-; global descriptor table (GDT)
-;-----------------------------------------------------------------------------;
-
- align 16
-
-public GDT_BASE
-GDT_BASE:
-; null descriptor
-NULL_SEL equ $-GDT_BASE ; Selector [0]
- dw 0 ; limit 15:0
- dw 0 ; base 15:0
- db 0 ; base 23:16
- db 0 ; type
- db 0 ; limit 19:16, flags
- db 0 ; base 31:24
-
-; linear data segment descriptor
-LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 092h ; present, ring 0, data, expand-up, writable
- db 0CFh ; page-granular, 32-bit
- db 0
-
-; linear code segment descriptor
-LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 09Fh ; present, ring 0, data, expand-up, writable
- db 0CFh ; page-granular, 32-bit
- db 0
-
-; system data segment descriptor
-SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 093h ; present, ring 0, data, expand-up, writable
- db 0CFh ; page-granular, 32-bit
- db 0
-
-; system code segment descriptor
-SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 09Ah ; present, ring 0, data, expand-up, writable
- db 0CFh ; page-granular, 32-bit
- db 0
-
-; spare segment descriptor
-SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]
- dw 0 ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 0 ; present, ring 0, data, expand-up, writable
- db 0 ; page-granular, 32-bit
- db 0
-
-;
-; system data segment descriptor
-;
-SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A
- db 0CFh ; G | D | L | AVL | Segment [19..16]
- db 0
-
-;
-; system code segment descriptor
-;
-SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]
- dw 0FFFFh ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A
- db 0AFh ; G | D | L | AVL | Segment [19..16]
- db 0
-
-; spare segment descriptor
-SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]
- dw 0 ; limit 0xFFFFF
- dw 0 ; base 0
- db 0
- db 0 ; present, ring 0, data, expand-up, writable
- db 0 ; page-granular, 32-bit
- db 0
-
-GDT_END:
-
-;
-;
-;------------------------------------------------------------------------------
-; Generic IDT Vector Handlers for the Host. They are all the same so they
-; will compress really well.
-;
-; By knowing the return address for Vector 00 you can can calculate the
-; vector number by looking at the call CommonInterruptEntry return address.
-; (return address - AsmIdtVector00Base)/8 == IDT index
-;
-;------------------------------------------------------------------------------
-
-_AsmIdtVector00 PROC NEAR PUBLIC
- call CommonInterruptEntry
-_AsmIdtVector00 ENDP
-AsmIdtVector00Base PROC NEAR PUBLIC
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- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
- call CommonInterruptEntry
- nop
- nop
- nop
-AsmIdtVector00Base ENDP
-
-
-;---------------------------------------;
-; CommonInterruptEntry ;
-;---------------------------------------;
-; The follow algorithm is used for the common interrupt routine.
-; TBD: Save EFI_SYSTEM_CONTEXT_x64 on the stack per AP definition
-;
-;
-CommonInterruptEntry PROC NEAR PUBLIC
- cli
- jmp $
- iret
-
-CommonInterruptEntry ENDP
-
-END
-
+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
- VirtualMemory.c\r
- \r
-Abstract:\r
-\r
- x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
- Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
- enter Long Mode (x64 64-bit mode).\r
-\r
- While we make a 1:1 mapping (identity mapping) for all physical pages \r
- we still need to use the MTRR's to ensure that the cachability attirbutes\r
- for all memory regions is correct.\r
-\r
- The basic idea is to use 2MB page table entries where ever possible. If\r
- more granularity of cachability is required then 4K page tables are used.\r
-\r
- References:\r
- 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
- 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
- 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
- \r
---*/ \r
-\r
-#include "VirtualMemory.h"\r
-\r
-x64_MTRR_VARIABLE_RANGE *mMTRRVariableRange;\r
-x64_MTRR_FIXED_RANGE mMTRRFixedRange;\r
-\r
-\r
-//\r
-// Physial memory limit values for each of the 11 fixed MTRRs\r
-//\r
-UINTN mFixedRangeLimit[] = {\r
- 0x7FFFF, // Fixed MTRR #0 describes 0x00000..0x7FFFF\r
- 0x9FFFF, // Fixed MTRR #1 describes 0x80000..0x9FFFF\r
- 0xBFFFF, // Fixed MTRR #2 describes 0xA0000..0xBFFFF\r
- 0xC7FFF, // Fixed MTRR #3 describes 0xC0000..0xC7FFF\r
- 0xCFFFF, // Fixed MTRR #4 describes 0xC8000..0xCFFFF\r
- 0xD7FFF, // Fixed MTRR #5 describes 0xD0000..0xD7FFF\r
- 0xDFFFF, // Fixed MTRR #6 describes 0xD8000..0xDFFFF\r
- 0xE7FFF, // Fixed MTRR #7 describes 0xE0000..0xE7FFF\r
- 0xEFFFF, // Fixed MTRR #8 describes 0xE8000..0xEFFFF\r
- 0xF7FFF, // Fixed MTRR #9 describes 0xF0000..0xF7FFF\r
- 0xFFFFF // Fixed MTRR #10 describes 0xF8000..0xFFFFF\r
-};\r
-\r
-//\r
-// The size, in bits, of each of the 11 fixed MTRR.\r
-//\r
-UINTN mFixedRangeShift[] = {\r
- 16, // Fixed MTRR #0 describes 8, 64 KB ranges\r
- 14, // Fixed MTRR #1 describes 8, 16 KB ranges\r
- 14, // Fixed MTRR #2 describes 8, 16 KB ranges\r
- 12, // Fixed MTRR #3 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #4 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #5 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #6 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #7 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #8 describes 8, 4 KB ranges\r
- 12, // Fixed MTRR #9 describes 8, 4 KB ranges\r
- 12 // Fixed MTRR #10 describes 8, 4 KB ranges\r
-};\r
-\r
-\r
-UINTN mPowerOf2[] = {\r
- 1,\r
- 2,\r
- 4,\r
- 8,\r
- 16,\r
- 32,\r
- 64,\r
- 128,\r
- 256,\r
- 512\r
-};\r
-\r
-x64_MTRR_MEMORY_TYPE\r
-EfiGetMTRRMemoryType (\r
- IN EFI_PHYSICAL_ADDRESS Address\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Retrieves the memory type from the MTRR that describes a physical address.\r
-\r
-Arguments:\r
-\r
- VariableRange - Set of Variable MTRRs\r
-\r
- FixedRange - Set of Fixed MTRRs\r
-\r
- Address - The physical address for which the MTRR memory type is being retrieved\r
-\r
-Returns:\r
-\r
- The MTRR Memory Type for the physical memory specified by Address.\r
-\r
---*/\r
-{\r
- UINTN Index;\r
- UINTN TypeIndex;\r
- BOOLEAN Found;\r
- x64_MTRR_MEMORY_TYPE VariableType;\r
- EFI_PHYSICAL_ADDRESS MaskBase;\r
- EFI_PHYSICAL_ADDRESS PhysMask;\r
-\r
- //\r
- // If the MTRRs are disabled, then return the Uncached Memory Type\r
- //\r
- if (mMTRRFixedRange.DefaultType.Bits.E == 0) {\r
- return Uncached;\r
- }\r
-\r
- //\r
- // If the CPU supports Fixed MTRRs and the Fixed MTRRs are enabled, then \r
- // see if Address falls into one of the Fixed MTRRs\r
- //\r
- if (mMTRRFixedRange.Capabilities.Bits.FIX && mMTRRFixedRange.DefaultType.Bits.FE) {\r
- //\r
- // Loop though 11 fixed MTRRs\r
- //\r
- for (Index = 0; Index < 11; Index++) {\r
- //\r
- // Check for a matching range\r
- //\r
- if (Address <= mFixedRangeLimit[Index]) {\r
- //\r
- // Compute the offset address into the MTRR bu subtrating the base address of the MTRR\r
- //\r
- if (Index > 0) {\r
- Address = Address - (mFixedRangeLimit[Index-1] + 1);\r
- }\r
- //\r
- // Retrieve the index into the MTRR to extract the memory type. The range is 0..7\r
- //\r
- TypeIndex = (UINTN)RShiftU64 (Address, mFixedRangeShift[Index]);\r
- \r
- //\r
- // Retrieve and return the memory type for the matching range\r
- //\r
- return mMTRRFixedRange.Fixed[Index].Type[TypeIndex];\r
- }\r
- }\r
- }\r
-\r
- //\r
- // If Address was not found in a Fixed MTRR, then search the Variable MTRRs\r
- //\r
- for (Index = 0, Found = FALSE, VariableType = WriteBack; Index < mMTRRFixedRange.Capabilities.Bits.VCNT; Index++) {\r
- //\r
- // BugBug: __aullshr complier error\r
- //\r
- if ((mMTRRVariableRange[Index].PhysMask.Uint64 & 0x800) == 0x800) { \r
- //if (mMTRRVariableRange[Index].PhysMask.Bits.Valid == 1) {\r
- PhysMask = mMTRRVariableRange[Index].PhysMask.Uint64 & ~0xfff;\r
- MaskBase = PhysMask & (mMTRRVariableRange[Index].PhysBase.Uint64 & ~0xfff);\r
- if (MaskBase == (PhysMask & Address)) {\r
- //\r
- // Check to see how many matches we find\r
- //\r
- Found = TRUE;\r
- if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == Uncached) || (VariableType == Uncached)) {\r
- //\r
- // If any matching region uses UC, the memory region is UC\r
- //\r
- VariableType = Uncached;\r
- } else if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == WriteThrough) || (VariableType == WriteThrough)){\r
- //\r
- // If it's WT and WB then set it to WT. If it's WT and other type it's undefined\r
- //\r
- VariableType = WriteThrough;\r
- } else {\r
- VariableType = mMTRRVariableRange[Index].PhysBase.Bits.Type;\r
- }\r
- }\r
- }\r
- }\r
- \r
- if (Found) {\r
- return VariableType;\r
- }\r
-\r
- //\r
- // Address was not found in the Fixed or Variable MTRRs, so return the default memory type\r
- //\r
- return mMTRRFixedRange.DefaultType.Bits.Type;\r
-}\r
-\r
-\r
-BOOLEAN\r
-CanNotUse2MBPage (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Test to see if a 2MB aligned page has all the same attributes. If a 2MB page\r
- has more than one attibute type it needs to be split into multiple 4K pages.\r
-\r
-Arguments:\r
- BaseAddress - 2MB aligned address to check out\r
-\r
-Returns:\r
- TRUE - This 2MB address range (BaseAddress) can NOT be mapped by a 2MB page\r
- FALSE - This 2MB address range can be mapped by a 2MB page\r
-\r
---*/\r
-{\r
- UINTN Index;\r
- x64_MTRR_MEMORY_TYPE MemoryType;\r
- x64_MTRR_MEMORY_TYPE PreviousMemoryType;\r
- \r
- //\r
- // Address needs to be 2MB aligned\r
- //\r
- ASSERT ((BaseAddress & 0x1fffff) == 0);\r
-\r
- PreviousMemoryType = -1;\r
- for (Index = 0; Index < 512; Index++, BaseAddress += 0x1000) {\r
- MemoryType = EfiGetMTRRMemoryType (BaseAddress);\r
- if ((Index != 0) && (MemoryType != PreviousMemoryType)) {\r
- return TRUE;\r
- }\r
-\r
- PreviousMemoryType = MemoryType;\r
- }\r
-\r
- //\r
- // All the pages had the same type\r
- //\r
- return FALSE;\r
-}\r
-\r
-\r
-\r
-\r
-VOID\r
-Convert2MBPageTo4KPages ( \r
- IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
- IN EFI_PHYSICAL_ADDRESS PageAddress\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Convert a single 2MB page entry to 512 4K page entries. The attributes for \r
- the 4K pages are read from the MTRR registers.\r
-\r
-Arguments:\r
- PageDirectoryEntry2MB - Page directory entry for PageAddress\r
- PageAddress - 2MB algined address of region to convert\r
-\r
-Returns:\r
- None\r
-\r
---*/\r
-{\r
- EFI_PHYSICAL_ADDRESS Address;\r
- x64_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4k;\r
- x64_PAGE_TABLE_ENTRY_4K *PageTableEntry;\r
- UINTN Index1;\r
-\r
- //\r
- // Allocate the page table entry for the 4K pages\r
- //\r
- PageTableEntry = (x64_PAGE_TABLE_ENTRY_4K *) AllocatePages (1);\r
-\r
- ASSERT (PageTableEntry != NULL);\r
-\r
- //\r
- // Convert PageDirectoryEntry2MB into a 4K Page Directory\r
- //\r
- PageDirectoryEntry4k = (x64_PAGE_DIRECTORY_ENTRY_4K *)PageDirectoryEntry2MB;\r
- PageDirectoryEntry2MB->Uint64 = (UINT64)PageTableEntry;\r
- PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
- PageDirectoryEntry2MB->Bits.Present = 1;\r
- \r
- //\r
- // Fill in the 4K page entries with the attributes from the MTRRs\r
- //\r
- for (Index1 = 0, Address = PageAddress; Index1 < 512; Index1++, PageTableEntry++, Address += 0x1000) {\r
- PageTableEntry->Uint64 = (UINT64)Address;\r
- PageTableEntry->Bits.ReadWrite = 1;\r
- PageTableEntry->Bits.Present = 1;\r
- }\r
-}\r
-\r
-\r
-EFI_PHYSICAL_ADDRESS\r
-CreateIdentityMappingPageTables (\r
- IN UINT32 NumberOfProcessorPhysicalAddressBits\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Allocates and fills in the Page Directory and Page Table Entries to\r
- establish a 1:1 Virtual to Physical mapping for physical memory from\r
- 0 to 4GB. Memory above 4GB is not mapped. The MTRRs are used to \r
- determine the cachability of the physical memory regions\r
-\r
-Arguments:\r
-\r
- NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
- Limits the number of page table entries \r
- to the physical address space.\r
-\r
-Returns:\r
- EFI_OUT_OF_RESOURCES There are not enough resources to allocate the Page Tables\r
-\r
- EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
-\r
---*/\r
-{ \r
- EFI_PHYSICAL_ADDRESS PageAddress;\r
- UINTN Index;\r
- UINTN MaxBitsSupported;\r
- UINTN Index1;\r
- UINTN Index2;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMapLevel4Entry;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMap;\r
- x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageDirectoryPointerEntry;\r
- x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB;\r
-\r
-\r
- //\r
- // Page Table structure 4 level 4K, 3 level 2MB.\r
- //\r
- // PageMapLevel4Entry : bits 47-39\r
- // PageDirectoryPointerEntry : bits 38-30\r
- // Page Table 2MB : PageDirectoryEntry2M : bits 29-21\r
- // Page Table 4K : PageDirectoryEntry4K : bits 29 - 21\r
- // PageTableEntry : bits 20 - 12\r
- //\r
- // Strategy is to map every thing in the processor address space using \r
- // 2MB pages. If more granularity is required the 2MB page will get \r
- // converted to set of 4K pages. \r
- //\r
-\r
- //\r
- // By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.\r
- //\r
- PageMap = PageMapLevel4Entry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
- ASSERT (PageMap != NULL);\r
- PageAddress = 0;\r
-\r
- //\r
- // The number of page-map Level-4 Offset entries is based on the number of \r
- // physical address bits. Less than equal to 38 bits only takes one entry.\r
- // 512 entries represents 48 address bits. \r
- //\r
- if (NumberOfProcessorPhysicalAddressBits <= 38) {\r
- MaxBitsSupported = 1;\r
- } else {\r
- MaxBitsSupported = mPowerOf2[NumberOfProcessorPhysicalAddressBits - 39];\r
- }\r
-\r
- for (Index = 0; Index < MaxBitsSupported; Index++, PageMapLevel4Entry++) {\r
- //\r
- // Each PML4 entry points to a page of Page Directory Pointer entires.\r
- // So lets allocate space for them and fill them in in the Index1 loop.\r
- // \r
- PageDirectoryPointerEntry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
- ASSERT (PageDirectoryPointerEntry != NULL);\r
-\r
- //\r
- // Make a PML4 Entry\r
- //\r
- PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
- PageMapLevel4Entry->Bits.ReadWrite = 1;\r
- PageMapLevel4Entry->Bits.Present = 1;\r
-\r
- for (Index1 = 0; Index1 < 512; Index1++, PageDirectoryPointerEntry++) {\r
- //\r
- // Each Directory Pointer entries points to a page of Page Directory entires.\r
- // So lets allocate space for them and fill them in in the Index2 loop.\r
- // \r
- PageDirectoryEntry2MB = (x64_PAGE_TABLE_ENTRY_2M *) AllocatePages (1);\r
- ASSERT (PageDirectoryEntry2MB != NULL);\r
-\r
- //\r
- // Fill in a Page Directory Pointer Entries\r
- //\r
- PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry2MB;\r
- PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
- PageDirectoryPointerEntry->Bits.Present = 1;\r
-\r
- for (Index2 = 0; Index2 < 512; Index2++, PageDirectoryEntry2MB++, PageAddress += 0x200000) {\r
- //\r
- // Fill in the Page Directory entries\r
- //\r
- PageDirectoryEntry2MB->Uint64 = (UINT64)PageAddress;\r
- PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
- PageDirectoryEntry2MB->Bits.Present = 1;\r
- PageDirectoryEntry2MB->Bits.MustBe1 = 1;\r
-\r
- if (CanNotUse2MBPage (PageAddress)) {\r
- //\r
- // Check to see if all 2MB has the same mapping. If not convert\r
- // to 4K pages by adding the 4th level of page table entries\r
- //\r
- Convert2MBPageTo4KPages (PageDirectoryEntry2MB, PageAddress);\r
- }\r
- }\r
- }\r
- }\r
-\r
- //\r
- // For the PML4 entries we are not using fill in a null entry.\r
- // for now we just copy the first entry.\r
- //\r
- for (; Index < 512; Index++, PageMapLevel4Entry++) {\r
- // EfiCopyMem (PageMapLevel4Entry, PageMap, sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K));\r
- CopyMem (PageMapLevel4Entry,\r
- PageMap,\r
- sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K)\r
- );\r
- }\r
-\r
- return (EFI_PHYSICAL_ADDRESS)PageMap;\r
-}\r
-\r
+++ /dev/null
-/*++ \r
-\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
- VirtualMemory.h\r
- \r
-Abstract:\r
-\r
- x64 Long Mode Virtual Memory Management Definitions \r
-\r
- References:\r
- 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
- 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
- 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
- 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
---*/ \r
-#ifndef _VIRTUAL_MEMORY_H_\r
-#define _VIRTUAL_MEMORY_H_\r
-\r
-\r
-#pragma pack(1)\r
-\r
-//\r
-// Page-Map Level-4 Offset (PML4) and\r
-// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
-//\r
-\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Reserved:1; // Reserved\r
- UINT64 MustBeZero:2; // Must Be Zero\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // No Execute bit\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
-\r
-//\r
-// Page-Directory Offset 4K\r
-//\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Reserved:1; // Reserved\r
- UINT64 MustBeZero:1; // Must Be Zero\r
- UINT64 Reserved2:1; // Reserved\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // No Execute bit\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_PAGE_DIRECTORY_ENTRY_4K;\r
-\r
-//\r
-// Page Table Entry 4K\r
-//\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_PAGE_TABLE_ENTRY_4K;\r
-\r
-\r
-//\r
-// Page Table Entry 2MB\r
-//\r
-typedef union {\r
- struct {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
- UINT64 Available:3; // Available for use by system software\r
- UINT64 PAT:1; //\r
- UINT64 MustBeZero:8; // Must be zero;\r
- UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
- UINT64 AvabilableHigh:11; // Available for use by system software\r
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_PAGE_TABLE_ENTRY_2M;\r
-\r
-typedef union {\r
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 Reserved:57;\r
-} x64_PAGE_TABLE_ENTRY_COMMON;\r
-\r
-typedef union {\r
- x64_PAGE_TABLE_ENTRY_4K Page4k;\r
- x64_PAGE_TABLE_ENTRY_2M Page2Mb;\r
- x64_PAGE_TABLE_ENTRY_COMMON Common;\r
-} x64_PAGE_TABLE_ENTRY;\r
-\r
-//\r
-// MTRR Definitions\r
-//\r
-typedef enum {\r
- Uncached = 0,\r
- WriteCombining = 1,\r
- WriteThrough = 4,\r
- WriteProtected = 5,\r
- WriteBack = 6\r
-} x64_MTRR_MEMORY_TYPE;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 VCNT:8; // The number of Variable Range MTRRs\r
- UINT32 FIX:1; // 1=Fixed Range MTRRs supported. 0=Fixed Range MTRRs not supported\r
- UINT32 Reserved_0; // Reserved\r
- UINT32 WC:1; // Write combining memory type supported\r
- UINT32 Reserved_1:21; // Reserved\r
- UINT32 Reserved_2:32; // Reserved\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_MTRRCAP_MSR;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Type:8; // Default Memory Type\r
- UINT32 Reserved_0:2; // Reserved\r
- UINT32 FE:1; // 1=Fixed Range MTRRs enabled. 0=Fixed Range MTRRs disabled\r
- UINT32 E:1; // 1=MTRRs enabled, 0=MTRRs disabled\r
- UINT32 Reserved_1:20; // Reserved\r
- UINT32 Reserved_2:32; // Reserved\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_MTRR_DEF_TYPE_MSR;\r
-\r
-typedef union {\r
- UINT8 Type[8]; // The 8 Memory Type values in the 64-bit MTRR\r
- UINT64 Uint64; // The full 64-bit MSR\r
-} x64_MTRR_FIXED_RANGE_MSR;\r
-\r
-typedef struct {\r
- x64_MTRRCAP_MSR Capabilities; // MTRR Capabilities MSR value\r
- x64_MTRR_DEF_TYPE_MSR DefaultType; // Default Memory Type MSR Value\r
- x64_MTRR_FIXED_RANGE_MSR Fixed[11]; // The 11 Fixed MTRR MSR Values\r
-} x64_MTRR_FIXED_RANGE;\r
-\r
-\r
-typedef union {\r
- struct {\r
- UINT64 Type:8; // Memory Type\r
- UINT64 Reserved0:4; // Reserved\r
- UINT64 PhysBase:40; // The physical base address(bits 35..12) of the MTRR\r
- UINT64 Reserved1:12 ; // Reserved\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_MTRR_PHYSBASE_MSR;\r
-\r
-typedef union {\r
- struct {\r
- UINT64 Reserved0:11; // Reserved\r
- UINT64 Valid:1; // 1=MTRR is valid, 0=MTRR is not valid\r
- UINT64 PhysMask:40; // The physical address mask (bits 35..12) of the MTRR\r
- UINT64 Reserved1:12; // Reserved\r
- } Bits;\r
- UINT64 Uint64;\r
-} x64_MTRR_PHYSMASK_MSR;\r
-\r
-typedef struct {\r
- x64_MTRR_PHYSBASE_MSR PhysBase; // Variable MTRR Physical Base MSR\r
- x64_MTRR_PHYSMASK_MSR PhysMask; // Variable MTRR Physical Mask MSR\r
-} x64_MTRR_VARIABLE_RANGE;\r
-\r
-#pragma pack()\r
-\r
-x64_MTRR_MEMORY_TYPE\r
-EfiGetMTRRMemoryType (\r
- IN EFI_PHYSICAL_ADDRESS Address\r
- )\r
-;\r
-\r
-BOOLEAN\r
-CanNotUse2MBPage (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress\r
- )\r
-;\r
-\r
-VOID\r
-Convert2MBPageTo4KPages ( \r
- IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
- IN EFI_PHYSICAL_ADDRESS PageAddress\r
- )\r
-;\r
-\r
-EFI_PHYSICAL_ADDRESS\r
-CreateIdentityMappingPageTables (\r
- IN UINT32 NumberOfProcessorPhysicalAddressBits\r
- )\r
-;\r
-\r
-#endif \r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DxeIpl.dxs\r
+\r
+Abstract:\r
+\r
+ Dependency expression file for DXE Initial Program Loader PEIM.\r
+ \r
+--*/ \r
+\r
+#include <AutoGen.h>\r
+#include <PeimDepex.h>\r
+\r
+DEPENDENCY_START\r
+ EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID\r
+DEPENDENCY_END\r
+\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DxeIpl.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef __PEI_DXEIPL_H__\r
+#define __PEI_DXEIPL_H__\r
+\r
+#define STACK_SIZE 0x20000\r
+#define BSP_STORE_SIZE 0x4000\r
+\r
+extern BOOLEAN gInMemory;\r
+\r
+VOID\r
+SwitchIplStacks (\r
+ VOID *EntryPoint,\r
+ UINTN Parameter1,\r
+ UINTN Parameter2,\r
+ VOID *NewStack,\r
+ VOID *NewBsp\r
+ )\r
+;\r
+\r
+EFI_STATUS\r
+PeiFindFile (\r
+ IN UINT8 Type,\r
+ IN UINT16 SectionType,\r
+ OUT EFI_GUID *FileName,\r
+ OUT VOID **Pe32Data\r
+ )\r
+;\r
+\r
+EFI_STATUS\r
+PeiLoadFile (\r
+ IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader,\r
+ IN VOID *Pe32Data,\r
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
+ OUT UINT64 *ImageSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
+ )\r
+;\r
+\r
+\r
+EFI_STATUS\r
+CreateArchSpecificHobs (\r
+ OUT EFI_PHYSICAL_ADDRESS *BspStore\r
+ )\r
+;\r
+\r
+EFI_STATUS\r
+GetImageReadFunction (\r
+ IN PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
+ )\r
+;\r
+\r
+EFI_STATUS\r
+PeiImageRead (\r
+ IN VOID *FileHandle,\r
+ IN UINTN FileOffset,\r
+ IN OUT UINTN *ReadSize,\r
+ OUT VOID *Buffer\r
+ )\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DxeIplLoadFile (\r
+ IN EFI_PEI_FV_FILE_LOADER_PPI *This,\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
+ OUT UINT64 *ImageSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
+ );\r
+\r
+EFI_STATUS\r
+ShadowDxeIpl (\r
+ IN EFI_FFS_FILE_HEADER *DxeIpl,\r
+ IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DxeLoadCore (\r
+ IN EFI_DXE_IPL_PPI *This,\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
+ );\r
+\r
+EFI_STATUS\r
+PeiProcessFile (\r
+ IN UINT16 SectionType,\r
+ IN OUT EFI_FFS_FILE_HEADER **RealFfsFileHeader,\r
+ OUT VOID **Pe32Data\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeDxeIpl (\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+EFI_STATUS\r
+PeiLoadx64File (\r
+ IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader,\r
+ IN VOID *Pe32Data,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
+ OUT UINT64 *ImageSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
+ )\r
+;\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+CreateIdentityMappingPageTables (\r
+ IN UINT32 NumberOfProcessorPhysicalAddressBits\r
+ )\r
+;\r
+\r
+VOID\r
+ActivateLongMode (\r
+ IN EFI_PHYSICAL_ADDRESS PageTables, \r
+ IN EFI_PHYSICAL_ADDRESS HobStart,\r
+ IN EFI_PHYSICAL_ADDRESS Stack,\r
+ IN EFI_PHYSICAL_ADDRESS CodeEntryPoint1,\r
+ IN EFI_PHYSICAL_ADDRESS CodeEntryPoint2\r
+ );\r
+\r
+VOID\r
+LoadGo64Gdt();\r
+\r
+#endif\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<!--Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.-->\r
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">\r
+ <MsaHeader>\r
+ <ModuleName>DxeIplX64</ModuleName>\r
+ <ModuleType>PEIM</ModuleType>\r
+ <GuidValue>0c55bdf7-d71d-4962-8fcb-348773e48929</GuidValue>\r
+ <Version>1.0</Version>\r
+ <Abstract>Component description file for DxeIplX64 module</Abstract>\r
+ <Description>The responsibility of this module is to load the DXE Core from a Firmware Volume. This implementation i used to load a 64-bit DXE Core.</Description>\r
+ <Copyright>Copyright 2006, Intel Corporation</Copyright>\r
+ <License>All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
+ </MsaHeader>\r
+ <ModuleDefinitions>\r
+ <SupportedArchitectures>IA32</SupportedArchitectures>\r
+ <BinaryModule>false</BinaryModule>\r
+ <OutputFileBasename>DxeIplX64</OutputFileBasename>\r
+ </ModuleDefinitions>\r
+ <LibraryClassDefinitions>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>DebugLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PeimEntryPoint</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>BaseLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>HobLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PerformanceLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PeiServicesLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>ReportStatusCodeLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>CacheMaintenanceLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>EdkPeCoffLoaderLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>UefiDecompressLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>TianoDecompressLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>CustomDecompressLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>PeiServicesTablePointerLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>BaseMemoryLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>MemoryAllocationLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>EdkPeCoffLoaderX64Lib</Keyword>\r
+ </LibraryClass>\r
+ </LibraryClassDefinitions>\r
+ <SourceFiles>\r
+ <Filename>DxeIpl.dxs</Filename>\r
+ <Filename>DxeIpl.h</Filename>\r
+ <Filename>DxeLoadX64.c</Filename>\r
+ <Filename SupArchList="IA32">x64/ImageRead.c</Filename>\r
+ <Filename SupArchList="IA32">x64/LongMode.asm</Filename>\r
+ <Filename SupArchList="IA32">x64/DxeLoadFunc.c</Filename>\r
+ <Filename SupArchList="IA32">x64/VirtualMemory.h</Filename>\r
+ <Filename SupArchList="IA32">x64/VirtualMemory.c</Filename>\r
+ </SourceFiles>\r
+ <PackageDependencies>\r
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
+ <Package PackageGuid="B6EC423C-21D2-490D-85C6-DD5864EAA674"/>\r
+ </PackageDependencies>\r
+ <Protocols>\r
+ <Protocol Usage="ALWAYS_CONSUMED">\r
+ <ProtocolCName>gEfiDecompressProtocolGuid</ProtocolCName>\r
+ </Protocol>\r
+ <Protocol Usage="ALWAYS_CONSUMED">\r
+ <ProtocolCName>gEfiTianoDecompressProtocolGuid</ProtocolCName>\r
+ </Protocol>\r
+ <Protocol Usage="ALWAYS_CONSUMED">\r
+ <ProtocolCName>gEfiCustomizedDecompressProtocolGuid</ProtocolCName>\r
+ </Protocol>\r
+ </Protocols>\r
+ <PPIs>\r
+ <Ppi Usage="SOMETIMES_PRODUCED">\r
+ <PpiCName>gEfiDxeIplPpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_PRODUCED">\r
+ <PpiCName>gEfiPeiFvFileLoaderPpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_PRODUCED">\r
+ <PpiCName>gEfiEndOfPeiSignalPpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_CONSUMED">\r
+ <PpiCName>gEfiPeiRecoveryModulePpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_CONSUMED">\r
+ <PpiCName>gEfiPeiS3ResumePpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_CONSUMED">\r
+ <PpiCName>gEfiPeiSectionExtractionPpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="SOMETIMES_CONSUMED">\r
+ <PpiCName>gEfiPeiSecurityPpiGuid</PpiCName>\r
+ </Ppi>\r
+ <Ppi Usage="PRIVATE">\r
+ <PpiCName>gPeiInMemoryGuid</PpiCName>\r
+ </Ppi>\r
+ </PPIs>\r
+ <Guids>\r
+ <GuidCNames Usage="ALWAYS_CONSUMED">\r
+ <GuidCName>gEfiPeiPeCoffLoaderGuid</GuidCName>\r
+ </GuidCNames>\r
+ </Guids>\r
+ <Externs>\r
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
+ <Extern>\r
+ <ModuleEntryPoint>PeimInitializeDxeIpl</ModuleEntryPoint>\r
+ </Extern>\r
+ </Externs>\r
+</ModuleSurfaceArea>
\ No newline at end of file
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DxeLoad.c\r
+\r
+Abstract:\r
+\r
+ Last PEIM.\r
+ Responsibility of this module is to load the DXE Core from a Firmware Volume.\r
+\r
+--*/\r
+\r
+#include <DxeIpl.h>\r
+\r
+#pragma warning( disable : 4305 )\r
+\r
+BOOLEAN gInMemory = FALSE;\r
+\r
+//\r
+// GUID for EM64T\r
+//\r
+#define EFI_PPI_NEEDED_BY_DXE \\r
+ { \\r
+ 0x4d37da42, 0x3a0c, 0x4eda, 0xb9, 0xeb, 0xbc, 0x0e, 0x1d, 0xb4, 0x71, 0x3b \\r
+ }\r
+EFI_GUID mPpiNeededByDxeGuid = EFI_PPI_NEEDED_BY_DXE;\r
+\r
+//\r
+// Module Globals used in the DXE to PEI handoff\r
+// These must be module globals, so the stack can be switched\r
+//\r
+static EFI_DXE_IPL_PPI mDxeIplPpi = {\r
+ DxeLoadCore\r
+};\r
+\r
+static EFI_PEI_FV_FILE_LOADER_PPI mLoadFilePpi = {\r
+ DxeIplLoadFile\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mPpiLoadFile = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiFvFileLoaderPpiGuid,\r
+ &mLoadFilePpi\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiDxeIplPpiGuid,\r
+ &mDxeIplPpi\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mPpiPeiInMemory = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gPeiInMemoryGuid,\r
+ NULL\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mPpiSignal = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiEndOfPeiSignalPpiGuid,\r
+ NULL\r
+};\r
+\r
+DECOMPRESS_LIBRARY gEfiDecompress = {\r
+ UefiDecompressGetInfo,\r
+ UefiDecompress\r
+};\r
+\r
+DECOMPRESS_LIBRARY gTianoDecompress = {\r
+ TianoDecompressGetInfo,\r
+ TianoDecompress\r
+};\r
+\r
+DECOMPRESS_LIBRARY gCustomDecompress = {\r
+ CustomDecompressGetInfo,\r
+ CustomDecompress\r
+};\r
+\r
+STATIC\r
+UINTN\r
+GetOccupiedSize (\r
+ IN UINTN ActualSize,\r
+ IN UINTN Alignment\r
+ )\r
+{\r
+ UINTN OccupiedSize;\r
+\r
+ OccupiedSize = ActualSize;\r
+ while ((OccupiedSize & (Alignment - 1)) != 0) {\r
+ OccupiedSize++;\r
+ }\r
+\r
+ return OccupiedSize;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeDxeIpl (\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initializes the Dxe Ipl PPI\r
+\r
+Arguments:\r
+\r
+ FfsHeader - Pointer to FFS file header\r
+ PeiServices - General purpose services available to every PEIM.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
+ EFI_BOOT_MODE BootMode;\r
+\r
+ Status = PeiServicesGetBootMode (&BootMode);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = PeiServicesLocatePpi (\r
+ &gPeiInMemoryGuid,\r
+ 0,\r
+ NULL,\r
+ NULL\r
+ );\r
+\r
+ if (EFI_ERROR (Status) && (BootMode != BOOT_ON_S3_RESUME)) { \r
+ //\r
+ // The DxeIpl has not yet been shadowed\r
+ //\r
+ PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
+\r
+ //\r
+ // Shadow DxeIpl and then re-run its entry point\r
+ //\r
+ Status = ShadowDxeIpl (FfsHeader, PeiEfiPeiPeCoffLoader);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ } else {\r
+ if (BootMode != BOOT_ON_S3_RESUME) {\r
+ //\r
+ // The DxeIpl has been shadowed\r
+ //\r
+ gInMemory = TRUE;\r
+\r
+ //\r
+ // Install LoadFile PPI\r
+ //\r
+ Status = PeiServicesInstallPpi (&mPpiLoadFile);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+ //\r
+ // Install DxeIpl PPI\r
+ //\r
+ PeiServicesInstallPpi (&mPpiList);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DxeLoadCore (\r
+ IN EFI_DXE_IPL_PPI *This,\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Main entry point to last PEIM\r
+\r
+Arguments:\r
+\r
+ This - Entry point for DXE IPL PPI\r
+ PeiServices - General purpose services available to every PEIM.\r
+ HobList - Address to the Pei HOB list\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - DEX core was successfully loaded.\r
+ EFI_OUT_OF_RESOURCES - There are not enough resources to load DXE core.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS TopOfStack;\r
+ EFI_PHYSICAL_ADDRESS BaseOfStack;\r
+ EFI_PHYSICAL_ADDRESS BspStore;\r
+ EFI_GUID DxeCoreFileName;\r
+ VOID *DxeCorePe32Data;\r
+ EFI_PHYSICAL_ADDRESS DxeCoreAddress;\r
+ UINT64 DxeCoreSize;\r
+ EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;\r
+ EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
+ EFI_BOOT_MODE BootMode;\r
+ EFI_PEI_RECOVERY_MODULE_PPI *PeiRecovery;\r
+ EFI_PEI_S3_RESUME_PPI *S3Resume;\r
+ EFI_PHYSICAL_ADDRESS PageTables;\r
+ \r
+ TopOfStack = 0;\r
+ BaseOfStack = 0;\r
+ BspStore = 0;\r
+ Status = EFI_SUCCESS;\r
+\r
+ //\r
+ // if in S3 Resume, restore configure\r
+ //\r
+ Status = PeiServicesGetBootMode (&BootMode);\r
+\r
+ if (!EFI_ERROR (Status) && (BootMode == BOOT_ON_S3_RESUME)) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiS3ResumePpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&S3Resume\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = S3Resume->S3RestoreConfig (PeiServices);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ //\r
+ // Install the PEI Protocols that are shared between PEI and DXE\r
+ //\r
+#ifdef EFI_NT_EMULATOR\r
+ PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
+ ASSERT (PeiEfiPeiPeCoffLoader != NULL);\r
+#else\r
+ PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderX64Protocol ();\r
+#endif \r
+\r
+#if 0\r
+ Status = InstallEfiPeiPeCoffLoader64 (PeiServices, &PeiEfiPeiPeCoffLoader, NULL);\r
+ ASSERT_EFI_ERROR (Status);\r
+#endif\r
+ //\r
+ // Allocate 128KB for the Stack\r
+ //\r
+ PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r
+ ASSERT (BaseOfStack != 0);\r
+\r
+ //\r
+ // Compute the top of the stack we were allocated. Pre-allocate a 32 bytes\r
+ // for safety (PpisNeededByDxe and DxeCore).\r
+ //\r
+ TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
+\r
+ //\r
+ // Add architecture-specifc HOBs (including the BspStore HOB)\r
+ //\r
+ Status = CreateArchSpecificHobs (&BspStore);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // See if we are in crisis recovery\r
+ //\r
+ Status = PeiServicesGetBootMode (&BootMode);\r
+ if (!EFI_ERROR (Status) && (BootMode == BOOT_IN_RECOVERY_MODE)) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiRecoveryModulePpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&PeiRecovery\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = PeiRecovery->LoadRecoveryCapsule (PeiServices, PeiRecovery);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Find the DXE Core in a Firmware Volume\r
+ //\r
+ Status = PeiFindFile (\r
+ EFI_FV_FILETYPE_DXE_CORE,\r
+ EFI_SECTION_PE32,\r
+ &DxeCoreFileName,\r
+ &DxeCorePe32Data\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Transfer control to the DXE Core\r
+ // The handoff state is simply a pointer to the HOB list\r
+ //\r
+ // PEI_PERF_END (PeiServices, L"DxeIpl", NULL, 0);\r
+\r
+ Status = PeiServicesInstallPpi (&mPpiSignal);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA \\r
+ // memory, it may be corrupted when copying FV to high-end memory \r
+ LoadGo64Gdt();\r
+\r
+ //\r
+ // Limit to 36 bits of addressing for debug. Should get it from CPU\r
+ //\r
+ PageTables = CreateIdentityMappingPageTables (36);\r
+\r
+\r
+ //\r
+ // Load the DXE Core from a Firmware Volume\r
+ //\r
+ Status = PeiLoadx64File (\r
+ PeiEfiPeiPeCoffLoader,\r
+ DxeCorePe32Data,\r
+ EfiBootServicesData,\r
+ &DxeCoreAddress,\r
+ &DxeCoreSize,\r
+ &DxeCoreEntryPoint\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ //\r
+ // Add HOB for the DXE Core\r
+ //\r
+ BuildModuleHob (\r
+ &DxeCoreFileName,\r
+ DxeCoreAddress,\r
+ DxeCoreSize,\r
+ DxeCoreEntryPoint\r
+ );\r
+\r
+ //\r
+ // Report Status Code EFI_SW_PEI_PC_HANDOFF_TO_NEXT\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_PROGRESS_CODE,\r
+ EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT\r
+ );\r
+\r
+ DEBUG ((EFI_D_INFO, "DXE Core Entry\n"));\r
+ //\r
+ // Go to Long Mode. Interrupts will not get turned on until the CPU AP is loaded.\r
+ // Call x64 drivers passing in single argument, a pointer to the HOBs.\r
+ //\r
+ ActivateLongMode (\r
+ PageTables, \r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw), \r
+ TopOfStack,\r
+ 0x00000000,\r
+ DxeCoreEntryPoint\r
+ );\r
+\r
+ //\r
+ // If we get here, then the DXE Core returned. This is an error\r
+ //\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_OUT_OF_RESOURCES;\r
+}\r
+\r
+EFI_STATUS\r
+PeiFindFile (\r
+ IN UINT8 Type,\r
+ IN UINT16 SectionType,\r
+ OUT EFI_GUID *FileName,\r
+ OUT VOID **Pe32Data\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Finds a PE/COFF of a specific Type and SectionType in the Firmware Volumes\r
+ described in the HOB list. Able to search in a compression set in a FFS file.\r
+ But only one level of compression is supported, that is, not able to search\r
+ in a compression set that is within another compression set.\r
+\r
+Arguments:\r
+\r
+ Type - The Type of file to retrieve\r
+\r
+ SectionType - The type of section to retrieve from a file\r
+\r
+ FileName - The name of the file found in the Firmware Volume\r
+\r
+ Pe32Data - Pointer to the beginning of the PE/COFF file found in the Firmware Volume\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The file was found, and the name is returned in FileName, and a pointer to\r
+ the PE/COFF image is returned in Pe32Data\r
+\r
+ EFI_NOT_FOUND - The file was not found in the Firmware Volumes present in the HOB List\r
+\r
+--*/\r
+{\r
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
+ EFI_FFS_FILE_HEADER *FfsFileHeader;\r
+ VOID *SectionData;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+\r
+\r
+ FwVolHeader = NULL;\r
+ FfsFileHeader = NULL;\r
+ SectionData = NULL;\r
+\r
+ //\r
+ // Foreach Firmware Volume, look for a specified type\r
+ // of file and break out when one is found\r
+ //\r
+ Hob.Raw = GetHobList ();\r
+ while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_FV, Hob.Raw)) != NULL) {\r
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) (Hob.FirmwareVolume->BaseAddress);\r
+ Status = PeiServicesFfsFindNextFile (\r
+ Type,\r
+ FwVolHeader,\r
+ &FfsFileHeader\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = PeiProcessFile (\r
+ SectionType,\r
+ &FfsFileHeader,\r
+ Pe32Data\r
+ );\r
+ CopyMem (FileName, &FfsFileHeader->Name, sizeof (EFI_GUID));\r
+ return Status;\r
+ }\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+EFI_STATUS\r
+PeiLoadx64File (\r
+ IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader,\r
+ IN VOID *Pe32Data,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
+ OUT UINT64 *ImageSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Loads and relocates a PE/COFF image into memory.\r
+\r
+Arguments:\r
+\r
+ PeiEfiPeiPeCoffLoader - Pointer to a PE COFF loader protocol\r
+\r
+ Pe32Data - The base address of the PE/COFF file that is to be loaded and relocated\r
+\r
+ ImageAddress - The base address of the relocated PE/COFF image\r
+\r
+ ImageSize - The size of the relocated PE/COFF image\r
+\r
+ EntryPoint - The entry point of the relocated PE/COFF image\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The file was loaded and relocated\r
+ EFI_OUT_OF_RESOURCES - There was not enough memory to load and relocate the PE/COFF file\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+ EFI_PHYSICAL_ADDRESS MemoryBuffer;\r
+\r
+ ZeroMem (&ImageContext, sizeof (ImageContext));\r
+ ImageContext.Handle = Pe32Data;\r
+ Status = GetImageReadFunction (&ImageContext);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = PeiEfiPeiPeCoffLoader->GetImageInfo (PeiEfiPeiPeCoffLoader, &ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // Allocate Memory for the image\r
+ //\r
+ //\r
+ // Allocate Memory for the image\r
+ //\r
+ PeiServicesAllocatePages (MemoryType, EFI_SIZE_TO_PAGES ((UINT32) ImageContext.ImageSize), &MemoryBuffer);\r
+ ImageContext.ImageAddress = MemoryBuffer;\r
+ ASSERT (ImageContext.ImageAddress != 0);\r
+\r
+ //\r
+ // Load the image to our new buffer\r
+ //\r
+\r
+ Status = PeiEfiPeiPeCoffLoader->LoadImage (PeiEfiPeiPeCoffLoader, &ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ \r
+ //\r
+ // Relocate the image in our new buffer\r
+ //\r
+ Status = PeiEfiPeiPeCoffLoader->RelocateImage (PeiEfiPeiPeCoffLoader, &ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Flush the instruction cache so the image data is written before we execute it\r
+ //\r
+ InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);\r
+\r
+ *ImageAddress = ImageContext.ImageAddress;\r
+ *ImageSize = ImageContext.ImageSize;\r
+ *EntryPoint = ImageContext.EntryPoint;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+ShadowDxeIpl (\r
+ IN EFI_FFS_FILE_HEADER *DxeIplFileHeader,\r
+ IN EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Shadow the DXE IPL to a different memory location. This occurs after permanent\r
+ memory has been discovered.\r
+\r
+Arguments:\r
+\r
+ DxeIplFileHeader - Pointer to the FFS file header of the DXE IPL driver\r
+\r
+ PeiEfiPeiPeCoffLoader - Pointer to a PE COFF loader protocol\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - DXE IPL was successfully shadowed to a different memory location.\r
+\r
+ EFI_ ERROR - The shadow was unsuccessful.\r
+\r
+\r
+--*/\r
+{\r
+ UINTN SectionLength;\r
+ UINTN OccupiedSectionLength;\r
+ EFI_PHYSICAL_ADDRESS DxeIplAddress;\r
+ UINT64 DxeIplSize;\r
+ EFI_PHYSICAL_ADDRESS DxeIplEntryPoint;\r
+ EFI_STATUS Status;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+\r
+ Section = (EFI_COMMON_SECTION_HEADER *) (DxeIplFileHeader + 1);\r
+\r
+ while ((Section->Type != EFI_SECTION_PE32) && (Section->Type != EFI_SECTION_TE)) {\r
+ SectionLength = *(UINT32 *) (Section->Size) & 0x00ffffff;\r
+ OccupiedSectionLength = GetOccupiedSize (SectionLength, 4);\r
+ Section = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) Section + OccupiedSectionLength);\r
+ }\r
+ \r
+ //\r
+ // Relocate DxeIpl into memory by using loadfile service\r
+ //\r
+ Status = PeiLoadx64File (\r
+ PeiEfiPeiPeCoffLoader,\r
+ (VOID *) (Section + 1),\r
+ EfiBootServicesData,\r
+ &DxeIplAddress,\r
+ &DxeIplSize,\r
+ &DxeIplEntryPoint\r
+ );\r
+ \r
+ if (Status == EFI_SUCCESS) {\r
+ //\r
+ // Install PeiInMemory to indicate the Dxeipl is shadowed\r
+ //\r
+ Status = PeiServicesInstallPpi (&mPpiPeiInMemory);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = ((EFI_PEIM_ENTRY_POINT) (UINTN) DxeIplEntryPoint) (DxeIplFileHeader, GetPeiServicesTablePointer());\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DxeIplLoadFile (\r
+ IN EFI_PEI_FV_FILE_LOADER_PPI *This,\r
+ IN EFI_FFS_FILE_HEADER *FfsHeader,\r
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,\r
+ OUT UINT64 *ImageSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Given a pointer to an FFS file containing a PE32 image, get the\r
+ information on the PE32 image, and then "load" it so that it\r
+ can be executed.\r
+\r
+Arguments:\r
+\r
+ This - pointer to our file loader protocol\r
+ FfsHeader - pointer to the FFS file header of the FFS file that\r
+ contains the PE32 image we want to load\r
+ ImageAddress - returned address where the PE32 image is loaded\r
+ ImageSize - returned size of the loaded PE32 image\r
+ EntryPoint - entry point to the loaded PE32 image\r
+\r
+Returns:\r
+ \r
+ EFI_SUCCESS - The FFS file was successfully loaded.\r
+ EFI_ERROR - Unable to load the FFS file.\r
+\r
+--*/\r
+{\r
+ EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeiEfiPeiPeCoffLoader;\r
+ EFI_STATUS Status;\r
+ VOID *Pe32Data;\r
+\r
+ Pe32Data = NULL;\r
+ PeiEfiPeiPeCoffLoader = (EFI_PEI_PE_COFF_LOADER_PROTOCOL *)GetPeCoffLoaderProtocol ();\r
+\r
+ //\r
+ // Preprocess the FFS file to get a pointer to the PE32 information\r
+ // in the enclosed PE32 image.\r
+ //\r
+ Status = PeiProcessFile (\r
+ EFI_SECTION_PE32,\r
+ &FfsHeader,\r
+ &Pe32Data\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // Load the PE image from the FFS file\r
+ //\r
+ Status = PeiLoadx64File (\r
+ PeiEfiPeiPeCoffLoader,\r
+ Pe32Data,\r
+ EfiBootServicesData,\r
+ ImageAddress,\r
+ ImageSize,\r
+ EntryPoint\r
+ );\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+PeiProcessFile (\r
+ IN UINT16 SectionType,\r
+ IN OUT EFI_FFS_FILE_HEADER **RealFfsFileHeader,\r
+ OUT VOID **Pe32Data\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+\r
+ SectionType - The type of section in the FFS file to process.\r
+\r
+ FfsFileHeader - Pointer to the FFS file to process, looking for the\r
+ specified SectionType\r
+\r
+ Pe32Data - returned pointer to the start of the PE32 image found\r
+ in the FFS file.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - found the PE32 section in the FFS file\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *SectionData;\r
+ DECOMPRESS_LIBRARY *DecompressLibrary;\r
+ UINT8 *DstBuffer;\r
+ UINT8 *ScratchBuffer;\r
+ UINT32 DstBufferSize;\r
+ UINT32 ScratchBufferSize;\r
+ EFI_COMMON_SECTION_HEADER *CmpSection;\r
+ UINTN CmpSectionLength;\r
+ UINTN OccupiedCmpSectionLength;\r
+ VOID *CmpFileData;\r
+ UINTN CmpFileSize;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+ UINTN SectionLength;\r
+ UINTN OccupiedSectionLength;\r
+ UINT64 FileSize;\r
+ EFI_GUID_DEFINED_SECTION *GuidedSectionHeader;\r
+ UINT32 AuthenticationStatus;\r
+ EFI_PEI_SECTION_EXTRACTION_PPI *SectionExtract;\r
+ UINT32 BufferSize;\r
+ UINT8 *Buffer;\r
+ EFI_PEI_SECURITY_PPI *Security;\r
+ BOOLEAN StartCrisisRecovery;\r
+ EFI_GUID TempGuid;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;\r
+ EFI_COMPRESSION_SECTION *CompressionSection;\r
+ EFI_FFS_FILE_HEADER *FfsFileHeader;\r
+ \r
+ FfsFileHeader = *RealFfsFileHeader;\r
+\r
+ Status = PeiServicesFfsFindSectionData (\r
+ EFI_SECTION_COMPRESSION,\r
+ FfsFileHeader,\r
+ &SectionData\r
+ );\r
+\r
+ //\r
+ // Upon finding a DXE Core file, see if there is first a compression section\r
+ //\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Yes, there is a compression section, so extract the contents\r
+ // Decompress the image here\r
+ //\r
+ Section = (EFI_COMMON_SECTION_HEADER *) (UINTN) (VOID *) ((UINT8 *) (FfsFileHeader) + (UINTN) sizeof (EFI_FFS_FILE_HEADER));\r
+\r
+ do {\r
+ SectionLength = *(UINT32 *) (Section->Size) & 0x00ffffff;\r
+ OccupiedSectionLength = GetOccupiedSize (SectionLength, 4);\r
+\r
+ //\r
+ // Was the DXE Core file encapsulated in a GUID'd section?\r
+ //\r
+ if (Section->Type == EFI_SECTION_GUID_DEFINED) {\r
+ //\r
+ // Locate the GUID'd Section Extractor\r
+ //\r
+ GuidedSectionHeader = (VOID *) (Section + 1);\r
+\r
+ //\r
+ // This following code constitutes the addition of the security model\r
+ // to the DXE IPL.\r
+ //\r
+ //\r
+ // Set a default authenticatino state\r
+ //\r
+ AuthenticationStatus = 0;\r
+\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiSectionExtractionPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&SectionExtract\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // Verify Authentication State\r
+ //\r
+ CopyMem (&TempGuid, Section + 1, sizeof (EFI_GUID));\r
+\r
+ Status = SectionExtract->PeiGetSection (\r
+ GetPeiServicesTablePointer(),\r
+ SectionExtract,\r
+ (EFI_SECTION_TYPE *) &SectionType,\r
+ &TempGuid,\r
+ 0,\r
+ (VOID **) &Buffer,\r
+ &BufferSize,\r
+ &AuthenticationStatus\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // If not ask the Security PPI, if exists, for disposition\r
+ //\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiSecurityPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&Security\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = Security->AuthenticationState (\r
+ GetPeiServicesTablePointer(),\r
+ (struct _EFI_PEI_SECURITY_PPI *) Security,\r
+ AuthenticationStatus,\r
+ FfsFileHeader,\r
+ &StartCrisisRecovery\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // If there is a security violation, report to caller and have\r
+ // the upper-level logic possible engender a crisis recovery\r
+ //\r
+ if (StartCrisisRecovery) {\r
+ return EFI_SECURITY_VIOLATION;\r
+ }\r
+ }\r
+\r
+ if (Section->Type == EFI_SECTION_PE32) {\r
+ //\r
+ // This is what we want\r
+ //\r
+ *Pe32Data = (VOID *) (Section + 1);\r
+ return EFI_SUCCESS;\r
+ } else if (Section->Type == EFI_SECTION_COMPRESSION) {\r
+ //\r
+ // This is a compression set, expand it\r
+ //\r
+ CompressionSection = (EFI_COMPRESSION_SECTION *) Section;\r
+\r
+ switch (CompressionSection->CompressionType) {\r
+ case EFI_STANDARD_COMPRESSION:\r
+ DecompressLibrary = &gTianoDecompress;\r
+ break;\r
+\r
+ case EFI_CUSTOMIZED_COMPRESSION:\r
+ //\r
+ // Load user customized compression protocol.\r
+ //\r
+ DecompressLibrary = &gCustomDecompress;\r
+ break;\r
+\r
+ case EFI_NOT_COMPRESSED:\r
+ default:\r
+ //\r
+ // Need to support not compressed file\r
+ //\r
+ ASSERT_EFI_ERROR (Status);\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ Status = DecompressLibrary->GetInfo (\r
+ (UINT8 *) ((EFI_COMPRESSION_SECTION *) Section + 1),\r
+ (UINT32) SectionLength - sizeof (EFI_COMPRESSION_SECTION),\r
+ &DstBufferSize,\r
+ &ScratchBufferSize\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // GetInfo failed\r
+ //\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Allocate scratch buffer\r
+ //\r
+ ScratchBuffer = AllocatePages (EFI_SIZE_TO_PAGES (ScratchBufferSize));\r
+ if (ScratchBuffer == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ //\r
+ // Allocate destination buffer\r
+ //\r
+ DstBuffer = AllocatePages (EFI_SIZE_TO_PAGES (DstBufferSize));\r
+ if (DstBuffer == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ //\r
+ // Call decompress function\r
+ //\r
+ Status = DecompressLibrary->Decompress (\r
+ (CHAR8 *) ((EFI_COMPRESSION_SECTION *) Section + 1),\r
+ DstBuffer,\r
+ ScratchBuffer\r
+ );\r
+\r
+ CmpSection = (EFI_COMMON_SECTION_HEADER *) DstBuffer;\r
+ if (CmpSection->Type == EFI_SECTION_RAW) {\r
+ //\r
+ // Skip the section header and\r
+ // adjust the pointer alignment to 16\r
+ //\r
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (DstBuffer + 16);\r
+\r
+ if (FvHeader->Signature == EFI_FVH_SIGNATURE) {\r
+ FfsFileHeader = NULL;\r
+ BuildFvHob ((EFI_PHYSICAL_ADDRESS) (UINTN) FvHeader, FvHeader->FvLength);\r
+ Status = PeiServicesFfsFindNextFile (\r
+ EFI_FV_FILETYPE_DXE_CORE,\r
+ FvHeader,\r
+ &FfsFileHeader\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Reture the FfsHeader that contain Pe32Data.\r
+ //\r
+ *RealFfsFileHeader = FfsFileHeader;\r
+ return PeiProcessFile (SectionType, RealFfsFileHeader, Pe32Data);\r
+ }\r
+ }\r
+ //\r
+ // Decompress successfully.\r
+ // Loop the decompressed data searching for expected section.\r
+ //\r
+ CmpFileData = (VOID *) DstBuffer;\r
+ CmpFileSize = DstBufferSize;\r
+ do {\r
+ CmpSectionLength = *(UINT32 *) (CmpSection->Size) & 0x00ffffff;\r
+ if (CmpSection->Type == EFI_SECTION_PE32) {\r
+ //\r
+ // This is what we want\r
+ //\r
+ *Pe32Data = (VOID *) (CmpSection + 1);\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ OccupiedCmpSectionLength = GetOccupiedSize (CmpSectionLength, 4);\r
+ CmpSection = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) CmpSection + OccupiedCmpSectionLength);\r
+ } while (CmpSection->Type != 0 && (UINTN) ((UINT8 *) CmpSection - (UINT8 *) CmpFileData) < CmpFileSize);\r
+ }\r
+\r
+ Section = (EFI_COMMON_SECTION_HEADER *) ((UINT8 *) Section + OccupiedSectionLength);\r
+ FileSize = FfsFileHeader->Size[0] & 0xFF;\r
+ FileSize += (FfsFileHeader->Size[1] << 8) & 0xFF00;\r
+ FileSize += (FfsFileHeader->Size[2] << 16) & 0xFF0000;\r
+ FileSize &= 0x00FFFFFF;\r
+ } while (Section->Type != 0 && (UINTN) ((UINT8 *) Section - (UINT8 *) FfsFileHeader) < FileSize);\r
+\r
+ //\r
+ // End of the decompression activity\r
+ //\r
+ } else {\r
+\r
+ Status = PeiServicesFfsFindSectionData (\r
+ EFI_SECTION_PE32,\r
+ FfsFileHeader,\r
+ &SectionData\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ Status = PeiServicesFfsFindSectionData (\r
+ EFI_SECTION_TE,\r
+ FfsFileHeader,\r
+ &SectionData\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+ }\r
+\r
+ *Pe32Data = SectionData;\r
+\r
+ return EFI_SUCCESS;\r
+}
\ No newline at end of file
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DxeLoadFunc.c\r
+\r
+Abstract:\r
+\r
+ Ia32-specifc functionality for DxeLoad X64 Lakeport.\r
+\r
+--*/\r
+\r
+#include <DxeIpl.h>\r
+\r
+EFI_STATUS\r
+CreateArchSpecificHobs (\r
+ OUT EFI_PHYSICAL_ADDRESS *BspStore\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Creates architecture-specific HOBs.\r
+\r
+ Note: New parameters should NOT be added for any HOBs that are added to this\r
+ function. BspStore is a special case because it is required for the\r
+ call to SwitchStacks() in DxeLoad().\r
+\r
+Arguments:\r
+\r
+ PeiServices - General purpose services available to every PEIM.\r
+ BspStore - The address of the BSP Store for those architectures that need\r
+ it. Otherwise 0.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The HOBs were created successfully.\r
+\r
+--*/\r
+{\r
+ *BspStore = 0;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ ImageRead.c\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#include <DxeIpl.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeiImageRead (\r
+ IN VOID *FileHandle,\r
+ IN UINTN FileOffset,\r
+ IN OUT UINTN *ReadSize,\r
+ OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Support routine for the PE/COFF Loader that reads a buffer from a PE/COFF file\r
+\r
+Arguments:\r
+\r
+ FileHandle - The handle to the PE/COFF file\r
+\r
+ FileOffset - The offset, in bytes, into the file to read\r
+\r
+ ReadSize - The number of bytes to read from the file starting at FileOffset\r
+\r
+ Buffer - A pointer to the buffer to read the data into.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - ReadSize bytes of data were read into Buffer from the PE/COFF file starting at FileOffset\r
+\r
+--*/\r
+{\r
+ CHAR8 *Destination8;\r
+ CHAR8 *Source8;\r
+ UINTN Length;\r
+\r
+ Destination8 = Buffer;\r
+ Source8 = (CHAR8 *) ((UINTN) FileHandle + FileOffset);\r
+ Length = *ReadSize;\r
+ while (Length--) {\r
+ *(Destination8++) = *(Source8++);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetImageReadFunction (\r
+ IN PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Support routine to return the PE32 Image Reader.\r
+ If the PeiImageRead() function is less than a page\r
+ in legnth. If the function is more than a page the DXE IPL will crash!!!!\r
+\r
+Arguments:\r
+ ImageContext - The context of the image being loaded\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - If Image function location is found\r
+\r
+--*/\r
+{\r
+ VOID *MemoryBuffer;\r
+\r
+ if (gInMemory) {\r
+ ImageContext->ImageRead = PeiImageRead;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // BugBug; This code assumes PeiImageRead() is less than a page in size!\r
+ // Allocate a page so we can shaddow the read function from FLASH into \r
+ // memory to increase performance. \r
+ //\r
+ \r
+ MemoryBuffer = AllocateCopyPool (0x400, (VOID *)(UINTN) PeiImageRead);\r
+ ASSERT (MemoryBuffer != NULL);\r
+\r
+ ImageContext->ImageRead = (PE_COFF_LOADER_READ_FILE) (UINTN) MemoryBuffer;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+ TITLE LongMode.asm: Assembly code for the entering long mode
+
+;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2006, Intel Corporation
+;* All rights reserved. This program and the accompanying materials
+;* are licensed and made available under the terms and conditions of the BSD License
+;* which accompanies this distribution. The full text of the license may be found at
+;* http://opensource.org/licenses/bsd-license.php
+;*
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;*
+;* LongMode.asm
+;*
+;* Abstract:
+;*
+;* Transition from 32-bit protected mode EFI environment into x64
+;* 64-bit bit long mode.
+;*
+;------------------------------------------------------------------------------
+
+.686p
+.model flat
+
+;
+; Create the exception handler code in IA32 C code
+;
+
+.code
+.stack
+.MMX
+.XMM
+
+_LoadGo64Gdt PROC Near Public
+ push ebp ; C prolog
+ push edi
+ mov ebp, esp
+ ;
+ ; Disable interrupts
+ ;
+ cli
+ ;
+ ; Reload the selectors
+ ; Note:
+ ; Make the Selectors 64-bit ready
+ ;
+ mov edi, OFFSET gdtr ; Load GDT register
+ mov ax,cs ; Get the selector data from our code image
+ mov es,ax
+ lgdt FWORD PTR es:[edi] ; and update the GDTR
+
+ db 067h
+ db 0eah ; Far Jump Offset:Selector to reload CS
+ dd OFFSET DataSelectorRld; Offset is ensuing instruction boundary
+ dw LINEAR_CODE_SEL ; Selector is our code selector, 10h
+DataSelectorRld::
+ mov ax, SYS_DATA_SEL ; Update the Base for the new selectors, too
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ pop edi
+ pop ebp
+ ret
+_LoadGo64Gdt endp
+
+
+; VOID
+; ActivateLongMode (
+; IN EFI_PHYSICAL_ADDRESS PageTables,
+; IN EFI_PHYSICAL_ADDRESS HobStart,
+; IN EFI_PHYSICAL_ADDRESS Stack,
+; IN EFI_PHYSICAL_ADDRESS PpisNeededByDxeIplEntryPoint,
+; IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint
+; )
+;
+; Input: [ebp][0h] = Original ebp
+; [ebp][4h] = Return address
+; [ebp][8h] = PageTables
+; [ebp][10h] = HobStart
+; [ebp][18h] = Stack
+; [ebp][20h] = CodeEntryPoint1 <--- Call this first (for each call, pass HOB pointer)
+; [ebp][28h] = CodeEntryPoint2 <--- Call this second
+;
+;
+_ActivateLongMode PROC Near Public
+ push ebp ; C prolog
+ mov ebp, esp
+
+ ;
+ ; Use CPUID to determine if the processor supports long mode.
+ ;
+ mov eax, 80000000h ; Extended-function code 8000000h.
+ cpuid ; Is largest extended function
+ cmp eax, 80000000h ; any function > 80000000h?
+ jbe no_long_mode ; If not, no long mode.
+ mov eax, 80000001h ; Extended-function code 8000001h.
+ cpuid ; Now EDX = extended-features flags.
+ bt edx, 29 ; Test if long mode is supported.
+ jnc no_long_mode ; Exit if not supported.
+
+ ;
+ ; Enable the 64-bit page-translation-table entries by
+ ; setting CR4.PAE=1 (this is _required_ before activating
+ ; long mode). Paging is not enabled until after long mode
+ ; is enabled.
+ ;
+ mov eax, cr4
+ bts eax, 5
+ mov cr4, eax
+
+ ;
+ ; Get the long-mode page tables, and initialize the
+ ; 64-bit CR3 (page-table base address) to point to the base
+ ; of the PML4 page table. The PML4 page table must be located
+ ; below 4 Gbytes because only 32 bits of CR3 are loaded when
+ ; the processor is not in 64-bit mode.
+ ;
+ mov eax, [ebp+8h] ; Get Page Tables
+ mov cr3, eax ; Initialize CR3 with PML4 base.
+
+ ;
+ ; Enable long mode (set EFER.LME=1).
+ ;
+ mov ecx, 0c0000080h ; EFER MSR number.
+ rdmsr ; Read EFER.
+ bts eax, 8 ; Set LME=1.
+ wrmsr ; Write EFER.
+
+ ;
+ ; Enable paging to activate long mode (set CR0.PG=1)
+ ;
+
+
+ mov eax, cr0 ; Read CR0.
+ bts eax, 31 ; Set PG=1.
+ mov cr0, eax ; Write CR0.
+ jmp go_to_long_mode
+go_to_long_mode:
+
+ ;
+ ; This is the next instruction after enabling paging. Jump to long mode
+ ;
+ db 067h
+ db 0eah ; Far Jump Offset:Selector to reload CS
+ dd OFFSET in_long_mode; Offset is ensuing instruction boundary
+ dw SYS_CODE64_SEL ; Selector is our code selector, 10h
+in_long_mode::
+ mov ax, SYS_DATA64_SEL
+ mov es, ax
+ mov ss, ax
+ mov ds, ax
+;; jmp $
+
+
+ ;
+ ; We're in long mode, so marshall the arguments to call the
+ ; passed in function pointers
+ ; Recall
+ ; [ebp][10h] = HobStart
+ ; [ebp][18h] = Stack
+ ; [ebp][20h] = PpisNeededByDxeIplEntryPoint <--- Call this first (for each call, pass HOB pointer)
+ ; [ebp][28h] = DxeCoreEntryPoint <--- Call this second
+ ;
+ db 48h
+ mov ebx, [ebp+18h] ; Setup the stack
+ db 48h
+ mov esp, ebx ; On a new stack now
+
+
+;; 00000905 FF D0 call rax
+
+ db 48h
+ mov ecx, [ebp+10h] ; Pass Hob Start in RCX
+ db 48h
+ mov eax, [ebp+28h] ; Get the function pointer for
+ ; DxeCoreEntryPoint into EAX
+
+;; 00000905 FF D0 call rax
+ db 0ffh
+ db 0d0h
+
+ ;
+ ; WE SHOULD NEVER GET HERE!!!!!!!!!!!!!
+ ;
+no_long_mode:
+ jmp no_long_mode
+_ActivateLongMode endp
+
+ align 16
+
+gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit
+ dd OFFSET GDT_BASE ; (GDT base gets set above)
+
+;-----------------------------------------------------------------------------;
+; global descriptor table (GDT)
+;-----------------------------------------------------------------------------;
+
+ align 16
+
+public GDT_BASE
+GDT_BASE:
+; null descriptor
+NULL_SEL equ $-GDT_BASE ; Selector [0]
+ dw 0 ; limit 15:0
+ dw 0 ; base 15:0
+ db 0 ; base 23:16
+ db 0 ; type
+ db 0 ; limit 19:16, flags
+ db 0 ; base 31:24
+
+; linear data segment descriptor
+LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 092h ; present, ring 0, data, expand-up, writable
+ db 0CFh ; page-granular, 32-bit
+ db 0
+
+; linear code segment descriptor
+LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 09Fh ; present, ring 0, data, expand-up, writable
+ db 0CFh ; page-granular, 32-bit
+ db 0
+
+; system data segment descriptor
+SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 093h ; present, ring 0, data, expand-up, writable
+ db 0CFh ; page-granular, 32-bit
+ db 0
+
+; system code segment descriptor
+SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 09Ah ; present, ring 0, data, expand-up, writable
+ db 0CFh ; page-granular, 32-bit
+ db 0
+
+; spare segment descriptor
+SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]
+ dw 0 ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 0 ; present, ring 0, data, expand-up, writable
+ db 0 ; page-granular, 32-bit
+ db 0
+
+;
+; system data segment descriptor
+;
+SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A
+ db 0CFh ; G | D | L | AVL | Segment [19..16]
+ db 0
+
+;
+; system code segment descriptor
+;
+SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]
+ dw 0FFFFh ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A
+ db 0AFh ; G | D | L | AVL | Segment [19..16]
+ db 0
+
+; spare segment descriptor
+SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]
+ dw 0 ; limit 0xFFFFF
+ dw 0 ; base 0
+ db 0
+ db 0 ; present, ring 0, data, expand-up, writable
+ db 0 ; page-granular, 32-bit
+ db 0
+
+GDT_END:
+
+;
+;
+;------------------------------------------------------------------------------
+; Generic IDT Vector Handlers for the Host. They are all the same so they
+; will compress really well.
+;
+; By knowing the return address for Vector 00 you can can calculate the
+; vector number by looking at the call CommonInterruptEntry return address.
+; (return address - AsmIdtVector00Base)/8 == IDT index
+;
+;------------------------------------------------------------------------------
+
+_AsmIdtVector00 PROC NEAR PUBLIC
+ call CommonInterruptEntry
+_AsmIdtVector00 ENDP
+AsmIdtVector00Base PROC NEAR PUBLIC
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+ call CommonInterruptEntry
+ nop
+ nop
+ nop
+AsmIdtVector00Base ENDP
+
+
+;---------------------------------------;
+; CommonInterruptEntry ;
+;---------------------------------------;
+; The follow algorithm is used for the common interrupt routine.
+; TBD: Save EFI_SYSTEM_CONTEXT_x64 on the stack per AP definition
+;
+;
+CommonInterruptEntry PROC NEAR PUBLIC
+ cli
+ jmp $
+ iret
+
+CommonInterruptEntry ENDP
+
+END
+
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ VirtualMemory.c\r
+ \r
+Abstract:\r
+\r
+ x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
+ Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
+ enter Long Mode (x64 64-bit mode).\r
+\r
+ While we make a 1:1 mapping (identity mapping) for all physical pages \r
+ we still need to use the MTRR's to ensure that the cachability attirbutes\r
+ for all memory regions is correct.\r
+\r
+ The basic idea is to use 2MB page table entries where ever possible. If\r
+ more granularity of cachability is required then 4K page tables are used.\r
+\r
+ References:\r
+ 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
+ 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
+ 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
+ \r
+--*/ \r
+\r
+#include "VirtualMemory.h"\r
+\r
+x64_MTRR_VARIABLE_RANGE *mMTRRVariableRange;\r
+x64_MTRR_FIXED_RANGE mMTRRFixedRange;\r
+\r
+\r
+//\r
+// Physial memory limit values for each of the 11 fixed MTRRs\r
+//\r
+UINTN mFixedRangeLimit[] = {\r
+ 0x7FFFF, // Fixed MTRR #0 describes 0x00000..0x7FFFF\r
+ 0x9FFFF, // Fixed MTRR #1 describes 0x80000..0x9FFFF\r
+ 0xBFFFF, // Fixed MTRR #2 describes 0xA0000..0xBFFFF\r
+ 0xC7FFF, // Fixed MTRR #3 describes 0xC0000..0xC7FFF\r
+ 0xCFFFF, // Fixed MTRR #4 describes 0xC8000..0xCFFFF\r
+ 0xD7FFF, // Fixed MTRR #5 describes 0xD0000..0xD7FFF\r
+ 0xDFFFF, // Fixed MTRR #6 describes 0xD8000..0xDFFFF\r
+ 0xE7FFF, // Fixed MTRR #7 describes 0xE0000..0xE7FFF\r
+ 0xEFFFF, // Fixed MTRR #8 describes 0xE8000..0xEFFFF\r
+ 0xF7FFF, // Fixed MTRR #9 describes 0xF0000..0xF7FFF\r
+ 0xFFFFF // Fixed MTRR #10 describes 0xF8000..0xFFFFF\r
+};\r
+\r
+//\r
+// The size, in bits, of each of the 11 fixed MTRR.\r
+//\r
+UINTN mFixedRangeShift[] = {\r
+ 16, // Fixed MTRR #0 describes 8, 64 KB ranges\r
+ 14, // Fixed MTRR #1 describes 8, 16 KB ranges\r
+ 14, // Fixed MTRR #2 describes 8, 16 KB ranges\r
+ 12, // Fixed MTRR #3 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #4 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #5 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #6 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #7 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #8 describes 8, 4 KB ranges\r
+ 12, // Fixed MTRR #9 describes 8, 4 KB ranges\r
+ 12 // Fixed MTRR #10 describes 8, 4 KB ranges\r
+};\r
+\r
+\r
+UINTN mPowerOf2[] = {\r
+ 1,\r
+ 2,\r
+ 4,\r
+ 8,\r
+ 16,\r
+ 32,\r
+ 64,\r
+ 128,\r
+ 256,\r
+ 512\r
+};\r
+\r
+x64_MTRR_MEMORY_TYPE\r
+EfiGetMTRRMemoryType (\r
+ IN EFI_PHYSICAL_ADDRESS Address\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Retrieves the memory type from the MTRR that describes a physical address.\r
+\r
+Arguments:\r
+\r
+ VariableRange - Set of Variable MTRRs\r
+\r
+ FixedRange - Set of Fixed MTRRs\r
+\r
+ Address - The physical address for which the MTRR memory type is being retrieved\r
+\r
+Returns:\r
+\r
+ The MTRR Memory Type for the physical memory specified by Address.\r
+\r
+--*/\r
+{\r
+ UINTN Index;\r
+ UINTN TypeIndex;\r
+ BOOLEAN Found;\r
+ x64_MTRR_MEMORY_TYPE VariableType;\r
+ EFI_PHYSICAL_ADDRESS MaskBase;\r
+ EFI_PHYSICAL_ADDRESS PhysMask;\r
+\r
+ //\r
+ // If the MTRRs are disabled, then return the Uncached Memory Type\r
+ //\r
+ if (mMTRRFixedRange.DefaultType.Bits.E == 0) {\r
+ return Uncached;\r
+ }\r
+\r
+ //\r
+ // If the CPU supports Fixed MTRRs and the Fixed MTRRs are enabled, then \r
+ // see if Address falls into one of the Fixed MTRRs\r
+ //\r
+ if (mMTRRFixedRange.Capabilities.Bits.FIX && mMTRRFixedRange.DefaultType.Bits.FE) {\r
+ //\r
+ // Loop though 11 fixed MTRRs\r
+ //\r
+ for (Index = 0; Index < 11; Index++) {\r
+ //\r
+ // Check for a matching range\r
+ //\r
+ if (Address <= mFixedRangeLimit[Index]) {\r
+ //\r
+ // Compute the offset address into the MTRR bu subtrating the base address of the MTRR\r
+ //\r
+ if (Index > 0) {\r
+ Address = Address - (mFixedRangeLimit[Index-1] + 1);\r
+ }\r
+ //\r
+ // Retrieve the index into the MTRR to extract the memory type. The range is 0..7\r
+ //\r
+ TypeIndex = (UINTN)RShiftU64 (Address, mFixedRangeShift[Index]);\r
+ \r
+ //\r
+ // Retrieve and return the memory type for the matching range\r
+ //\r
+ return mMTRRFixedRange.Fixed[Index].Type[TypeIndex];\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If Address was not found in a Fixed MTRR, then search the Variable MTRRs\r
+ //\r
+ for (Index = 0, Found = FALSE, VariableType = WriteBack; Index < mMTRRFixedRange.Capabilities.Bits.VCNT; Index++) {\r
+ //\r
+ // BugBug: __aullshr complier error\r
+ //\r
+ if ((mMTRRVariableRange[Index].PhysMask.Uint64 & 0x800) == 0x800) { \r
+ //if (mMTRRVariableRange[Index].PhysMask.Bits.Valid == 1) {\r
+ PhysMask = mMTRRVariableRange[Index].PhysMask.Uint64 & ~0xfff;\r
+ MaskBase = PhysMask & (mMTRRVariableRange[Index].PhysBase.Uint64 & ~0xfff);\r
+ if (MaskBase == (PhysMask & Address)) {\r
+ //\r
+ // Check to see how many matches we find\r
+ //\r
+ Found = TRUE;\r
+ if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == Uncached) || (VariableType == Uncached)) {\r
+ //\r
+ // If any matching region uses UC, the memory region is UC\r
+ //\r
+ VariableType = Uncached;\r
+ } else if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == WriteThrough) || (VariableType == WriteThrough)){\r
+ //\r
+ // If it's WT and WB then set it to WT. If it's WT and other type it's undefined\r
+ //\r
+ VariableType = WriteThrough;\r
+ } else {\r
+ VariableType = mMTRRVariableRange[Index].PhysBase.Bits.Type;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ if (Found) {\r
+ return VariableType;\r
+ }\r
+\r
+ //\r
+ // Address was not found in the Fixed or Variable MTRRs, so return the default memory type\r
+ //\r
+ return mMTRRFixedRange.DefaultType.Bits.Type;\r
+}\r
+\r
+\r
+BOOLEAN\r
+CanNotUse2MBPage (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Test to see if a 2MB aligned page has all the same attributes. If a 2MB page\r
+ has more than one attibute type it needs to be split into multiple 4K pages.\r
+\r
+Arguments:\r
+ BaseAddress - 2MB aligned address to check out\r
+\r
+Returns:\r
+ TRUE - This 2MB address range (BaseAddress) can NOT be mapped by a 2MB page\r
+ FALSE - This 2MB address range can be mapped by a 2MB page\r
+\r
+--*/\r
+{\r
+ UINTN Index;\r
+ x64_MTRR_MEMORY_TYPE MemoryType;\r
+ x64_MTRR_MEMORY_TYPE PreviousMemoryType;\r
+ \r
+ //\r
+ // Address needs to be 2MB aligned\r
+ //\r
+ ASSERT ((BaseAddress & 0x1fffff) == 0);\r
+\r
+ PreviousMemoryType = -1;\r
+ for (Index = 0; Index < 512; Index++, BaseAddress += 0x1000) {\r
+ MemoryType = EfiGetMTRRMemoryType (BaseAddress);\r
+ if ((Index != 0) && (MemoryType != PreviousMemoryType)) {\r
+ return TRUE;\r
+ }\r
+\r
+ PreviousMemoryType = MemoryType;\r
+ }\r
+\r
+ //\r
+ // All the pages had the same type\r
+ //\r
+ return FALSE;\r
+}\r
+\r
+\r
+\r
+\r
+VOID\r
+Convert2MBPageTo4KPages ( \r
+ IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
+ IN EFI_PHYSICAL_ADDRESS PageAddress\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Convert a single 2MB page entry to 512 4K page entries. The attributes for \r
+ the 4K pages are read from the MTRR registers.\r
+\r
+Arguments:\r
+ PageDirectoryEntry2MB - Page directory entry for PageAddress\r
+ PageAddress - 2MB algined address of region to convert\r
+\r
+Returns:\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_PHYSICAL_ADDRESS Address;\r
+ x64_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4k;\r
+ x64_PAGE_TABLE_ENTRY_4K *PageTableEntry;\r
+ UINTN Index1;\r
+\r
+ //\r
+ // Allocate the page table entry for the 4K pages\r
+ //\r
+ PageTableEntry = (x64_PAGE_TABLE_ENTRY_4K *) AllocatePages (1);\r
+\r
+ ASSERT (PageTableEntry != NULL);\r
+\r
+ //\r
+ // Convert PageDirectoryEntry2MB into a 4K Page Directory\r
+ //\r
+ PageDirectoryEntry4k = (x64_PAGE_DIRECTORY_ENTRY_4K *)PageDirectoryEntry2MB;\r
+ PageDirectoryEntry2MB->Uint64 = (UINT64)PageTableEntry;\r
+ PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry2MB->Bits.Present = 1;\r
+ \r
+ //\r
+ // Fill in the 4K page entries with the attributes from the MTRRs\r
+ //\r
+ for (Index1 = 0, Address = PageAddress; Index1 < 512; Index1++, PageTableEntry++, Address += 0x1000) {\r
+ PageTableEntry->Uint64 = (UINT64)Address;\r
+ PageTableEntry->Bits.ReadWrite = 1;\r
+ PageTableEntry->Bits.Present = 1;\r
+ }\r
+}\r
+\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+CreateIdentityMappingPageTables (\r
+ IN UINT32 NumberOfProcessorPhysicalAddressBits\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allocates and fills in the Page Directory and Page Table Entries to\r
+ establish a 1:1 Virtual to Physical mapping for physical memory from\r
+ 0 to 4GB. Memory above 4GB is not mapped. The MTRRs are used to \r
+ determine the cachability of the physical memory regions\r
+\r
+Arguments:\r
+\r
+ NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.\r
+ Limits the number of page table entries \r
+ to the physical address space.\r
+\r
+Returns:\r
+ EFI_OUT_OF_RESOURCES There are not enough resources to allocate the Page Tables\r
+\r
+ EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
+\r
+--*/\r
+{ \r
+ EFI_PHYSICAL_ADDRESS PageAddress;\r
+ UINTN Index;\r
+ UINTN MaxBitsSupported;\r
+ UINTN Index1;\r
+ UINTN Index2;\r
+ x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMapLevel4Entry;\r
+ x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMap;\r
+ x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageDirectoryPointerEntry;\r
+ x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB;\r
+\r
+\r
+ //\r
+ // Page Table structure 4 level 4K, 3 level 2MB.\r
+ //\r
+ // PageMapLevel4Entry : bits 47-39\r
+ // PageDirectoryPointerEntry : bits 38-30\r
+ // Page Table 2MB : PageDirectoryEntry2M : bits 29-21\r
+ // Page Table 4K : PageDirectoryEntry4K : bits 29 - 21\r
+ // PageTableEntry : bits 20 - 12\r
+ //\r
+ // Strategy is to map every thing in the processor address space using \r
+ // 2MB pages. If more granularity is required the 2MB page will get \r
+ // converted to set of 4K pages. \r
+ //\r
+\r
+ //\r
+ // By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.\r
+ //\r
+ PageMap = PageMapLevel4Entry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
+ ASSERT (PageMap != NULL);\r
+ PageAddress = 0;\r
+\r
+ //\r
+ // The number of page-map Level-4 Offset entries is based on the number of \r
+ // physical address bits. Less than equal to 38 bits only takes one entry.\r
+ // 512 entries represents 48 address bits. \r
+ //\r
+ if (NumberOfProcessorPhysicalAddressBits <= 38) {\r
+ MaxBitsSupported = 1;\r
+ } else {\r
+ MaxBitsSupported = mPowerOf2[NumberOfProcessorPhysicalAddressBits - 39];\r
+ }\r
+\r
+ for (Index = 0; Index < MaxBitsSupported; Index++, PageMapLevel4Entry++) {\r
+ //\r
+ // Each PML4 entry points to a page of Page Directory Pointer entires.\r
+ // So lets allocate space for them and fill them in in the Index1 loop.\r
+ // \r
+ PageDirectoryPointerEntry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);\r
+ ASSERT (PageDirectoryPointerEntry != NULL);\r
+\r
+ //\r
+ // Make a PML4 Entry\r
+ //\r
+ PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
+ PageMapLevel4Entry->Bits.ReadWrite = 1;\r
+ PageMapLevel4Entry->Bits.Present = 1;\r
+\r
+ for (Index1 = 0; Index1 < 512; Index1++, PageDirectoryPointerEntry++) {\r
+ //\r
+ // Each Directory Pointer entries points to a page of Page Directory entires.\r
+ // So lets allocate space for them and fill them in in the Index2 loop.\r
+ // \r
+ PageDirectoryEntry2MB = (x64_PAGE_TABLE_ENTRY_2M *) AllocatePages (1);\r
+ ASSERT (PageDirectoryEntry2MB != NULL);\r
+\r
+ //\r
+ // Fill in a Page Directory Pointer Entries\r
+ //\r
+ PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry2MB;\r
+ PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
+ PageDirectoryPointerEntry->Bits.Present = 1;\r
+\r
+ for (Index2 = 0; Index2 < 512; Index2++, PageDirectoryEntry2MB++, PageAddress += 0x200000) {\r
+ //\r
+ // Fill in the Page Directory entries\r
+ //\r
+ PageDirectoryEntry2MB->Uint64 = (UINT64)PageAddress;\r
+ PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry2MB->Bits.Present = 1;\r
+ PageDirectoryEntry2MB->Bits.MustBe1 = 1;\r
+\r
+ if (CanNotUse2MBPage (PageAddress)) {\r
+ //\r
+ // Check to see if all 2MB has the same mapping. If not convert\r
+ // to 4K pages by adding the 4th level of page table entries\r
+ //\r
+ Convert2MBPageTo4KPages (PageDirectoryEntry2MB, PageAddress);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // For the PML4 entries we are not using fill in a null entry.\r
+ // for now we just copy the first entry.\r
+ //\r
+ for (; Index < 512; Index++, PageMapLevel4Entry++) {\r
+ // EfiCopyMem (PageMapLevel4Entry, PageMap, sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K));\r
+ CopyMem (PageMapLevel4Entry,\r
+ PageMap,\r
+ sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K)\r
+ );\r
+ }\r
+\r
+ return (EFI_PHYSICAL_ADDRESS)PageMap;\r
+}\r
+\r
--- /dev/null
+/*++ \r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ VirtualMemory.h\r
+ \r
+Abstract:\r
+\r
+ x64 Long Mode Virtual Memory Management Definitions \r
+\r
+ References:\r
+ 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
+ 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
+ 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
+ 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
+--*/ \r
+#ifndef _VIRTUAL_MEMORY_H_\r
+#define _VIRTUAL_MEMORY_H_\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Page-Map Level-4 Offset (PML4) and\r
+// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
+//\r
+\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Reserved:1; // Reserved\r
+ UINT64 MustBeZero:2; // Must Be Zero\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // No Execute bit\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
+\r
+//\r
+// Page-Directory Offset 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Reserved:1; // Reserved\r
+ UINT64 MustBeZero:1; // Must Be Zero\r
+ UINT64 Reserved2:1; // Reserved\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // No Execute bit\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_PAGE_DIRECTORY_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_PAGE_TABLE_ENTRY_4K;\r
+\r
+\r
+//\r
+// Page Table Entry 2MB\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PAT:1; //\r
+ UINT64 MustBeZero:8; // Must be zero;\r
+ UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_PAGE_TABLE_ENTRY_2M;\r
+\r
+typedef union {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 Reserved:57;\r
+} x64_PAGE_TABLE_ENTRY_COMMON;\r
+\r
+typedef union {\r
+ x64_PAGE_TABLE_ENTRY_4K Page4k;\r
+ x64_PAGE_TABLE_ENTRY_2M Page2Mb;\r
+ x64_PAGE_TABLE_ENTRY_COMMON Common;\r
+} x64_PAGE_TABLE_ENTRY;\r
+\r
+//\r
+// MTRR Definitions\r
+//\r
+typedef enum {\r
+ Uncached = 0,\r
+ WriteCombining = 1,\r
+ WriteThrough = 4,\r
+ WriteProtected = 5,\r
+ WriteBack = 6\r
+} x64_MTRR_MEMORY_TYPE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 VCNT:8; // The number of Variable Range MTRRs\r
+ UINT32 FIX:1; // 1=Fixed Range MTRRs supported. 0=Fixed Range MTRRs not supported\r
+ UINT32 Reserved_0; // Reserved\r
+ UINT32 WC:1; // Write combining memory type supported\r
+ UINT32 Reserved_1:21; // Reserved\r
+ UINT32 Reserved_2:32; // Reserved\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_MTRRCAP_MSR;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Type:8; // Default Memory Type\r
+ UINT32 Reserved_0:2; // Reserved\r
+ UINT32 FE:1; // 1=Fixed Range MTRRs enabled. 0=Fixed Range MTRRs disabled\r
+ UINT32 E:1; // 1=MTRRs enabled, 0=MTRRs disabled\r
+ UINT32 Reserved_1:20; // Reserved\r
+ UINT32 Reserved_2:32; // Reserved\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_MTRR_DEF_TYPE_MSR;\r
+\r
+typedef union {\r
+ UINT8 Type[8]; // The 8 Memory Type values in the 64-bit MTRR\r
+ UINT64 Uint64; // The full 64-bit MSR\r
+} x64_MTRR_FIXED_RANGE_MSR;\r
+\r
+typedef struct {\r
+ x64_MTRRCAP_MSR Capabilities; // MTRR Capabilities MSR value\r
+ x64_MTRR_DEF_TYPE_MSR DefaultType; // Default Memory Type MSR Value\r
+ x64_MTRR_FIXED_RANGE_MSR Fixed[11]; // The 11 Fixed MTRR MSR Values\r
+} x64_MTRR_FIXED_RANGE;\r
+\r
+\r
+typedef union {\r
+ struct {\r
+ UINT64 Type:8; // Memory Type\r
+ UINT64 Reserved0:4; // Reserved\r
+ UINT64 PhysBase:40; // The physical base address(bits 35..12) of the MTRR\r
+ UINT64 Reserved1:12 ; // Reserved\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_MTRR_PHYSBASE_MSR;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT64 Reserved0:11; // Reserved\r
+ UINT64 Valid:1; // 1=MTRR is valid, 0=MTRR is not valid\r
+ UINT64 PhysMask:40; // The physical address mask (bits 35..12) of the MTRR\r
+ UINT64 Reserved1:12; // Reserved\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} x64_MTRR_PHYSMASK_MSR;\r
+\r
+typedef struct {\r
+ x64_MTRR_PHYSBASE_MSR PhysBase; // Variable MTRR Physical Base MSR\r
+ x64_MTRR_PHYSMASK_MSR PhysMask; // Variable MTRR Physical Mask MSR\r
+} x64_MTRR_VARIABLE_RANGE;\r
+\r
+#pragma pack()\r
+\r
+x64_MTRR_MEMORY_TYPE\r
+EfiGetMTRRMemoryType (\r
+ IN EFI_PHYSICAL_ADDRESS Address\r
+ )\r
+;\r
+\r
+BOOLEAN\r
+CanNotUse2MBPage (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress\r
+ )\r
+;\r
+\r
+VOID\r
+Convert2MBPageTo4KPages ( \r
+ IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
+ IN EFI_PHYSICAL_ADDRESS PageAddress\r
+ )\r
+;\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+CreateIdentityMappingPageTables (\r
+ IN UINT32 NumberOfProcessorPhysicalAddressBits\r
+ )\r
+;\r
+\r
+#endif \r
<Filename>Bus/Usb/UsbMouse/Dxe/UsbMouse.msa</Filename>\r
<Filename>Core/Dxe/DxeMain.msa</Filename>\r
<Filename>Core/DxeIplPeim/DxeIpl.msa</Filename>\r
- <Filename>Core/DxeIplPeim/DxeIplX64.msa</Filename>\r
+ <Filename>Core/DxeIplX64Peim/DxeIplX64.msa</Filename>\r
<Filename>Core/Pei/PeiMain.msa</Filename>\r
<Filename>Library/BaseCustomDecompressLibNull/BaseCustomDecompressLibNull.msa</Filename>\r
<Filename>Library/BaseUefiTianoDecompressLib/BaseUefiTianoDecompressLib.msa</Filename>\r
<Filename>Universal/Security/SecurityStub/Dxe/SecurityStub.msa</Filename>\r
<Filename>Universal/StatusCode/RuntimeDxe/StatusCode.msa</Filename>\r
<Filename>Universal/UserInterface/HiiDataBase/Dxe/HiiDatabase.msa</Filename>\r
- <Filename>Universal/UserInterface/SetupBrowser/Dxe/DriverSample/DriverSample.msa</Filename>\r
+ <Filename>Universal/UserInterface/DriverSample/DriverSample.msa</Filename>\r
<Filename>Universal/UserInterface/SetupBrowser/Dxe/SetupBrowser.msa</Filename>\r
<Filename>Universal/Variable/Pei/Variable.msa</Filename>\r
<Filename>Universal/EmuVariable/RuntimeDxe/EmuVariable.msa</Filename>\r
<ModuleType>DXE_DRIVER</ModuleType>\r
<GuidValue>ed3de5c8-c389-44f2-a35e-2ebdc9802a49</GuidValue>\r
<Version>1.0</Version>\r
- <Abstract>Component description file for the PEI library.</Abstract>\r
- <Description>FIX ME!</Description>\r
+ <Abstract>EdkPeCoffLoaderLib library instance</Abstract>\r
+ <Description>This library gets PeCoffLoader Protocol from Hob List</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation.</Copyright>\r
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
<ModuleType>PEIM</ModuleType>\r
<GuidValue>858bbbc9-474f-4556-a361-0ae52a44ffa5</GuidValue>\r
<Version>1.0</Version>\r
- <Abstract>Component description file for the PEI library.</Abstract>\r
- <Description>FIX ME!</Description>\r
+ <Abstract>EdkPeCoffLoaderLib library instance</Abstract>\r
+ <Description>This library provides PeCoffLoader protocol based on PeCoffLib functions.</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation.</Copyright>\r
<License>All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
<ModuleType>PEIM</ModuleType>\r
<GuidValue>6aac37f2-7b46-4ef3-8645-c24800a3d410</GuidValue>\r
<Version>1.0</Version>\r
- <Abstract>Component description file for the PEI library.</Abstract>\r
- <Description>FIX ME!</Description>\r
+ <Abstract>EdkPeCoffLoaderX64Lib library instance</Abstract>\r
+ <Description>This library provides PeCoffLoader protocol to support PE64 image.</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation.</Copyright>\r
<License>All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r