EmbeddedPkg: remove ISP 1716 USB host controller driver

[mirror_edk2.git] / EmbeddedPkg / Drivers / Isp1761UsbDxe / Isp1761UsbDxe.h

diff --git a/EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h b/EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h
deleted file mode 100644 (file)
index c4f1aab..0000000
--- a/EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/** @file\r
-\r
-  Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
-\r
-  SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef __ISP1761_USB_DXE_H__\r
-#define __ISP1761_USB_DXE_H__\r
-\r
-#define ISP1761_USB_BASE FixedPcdGet32 (PcdIsp1761BaseAddress)\r
-\r
-#define READ_REG32(Offset) MmioRead32 (ISP1761_USB_BASE + Offset)\r
-#define READ_REG16(Offset) (UINT16) READ_REG32 (Offset)\r
-#define WRITE_REG32(Offset, Val)  MmioWrite32 (ISP1761_USB_BASE + Offset, Val)\r
-#define WRITE_REG16(Offset, Val)  MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)\r
-#define WRITE_REG8(Offset, Val)   MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)\r
-\r
-// Max packet size in bytes (For Full Speed USB 64 is the only valid value)\r
-#define MAX_PACKET_SIZE_CONTROL     64\r
-\r
-#define MAX_PACKET_SIZE_BULK        512\r
-\r
-// 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer\r
-#define ISP1761_NUM_ENDPOINTS               16\r
-\r
-// Endpoint Indexes\r
-#define ISP1761_EP0SETUP                    0x20\r
-#define ISP1761_EP0RX                       0x00\r
-#define ISP1761_EP0TX                       0x01\r
-#define ISP1761_EP1RX                       0x02\r
-#define ISP1761_EP1TX                       0x03\r
-\r
-// DcInterrupt bits\r
-#define ISP1761_DC_INTERRUPT_BRESET         BIT0\r
-#define ISP1761_DC_INTERRUPT_SOF            BIT1\r
-#define ISP1761_DC_INTERRUPT_PSOF           BIT2\r
-#define ISP1761_DC_INTERRUPT_SUSP           BIT3\r
-#define ISP1761_DC_INTERRUPT_RESUME         BIT4\r
-#define ISP1761_DC_INTERRUPT_HS_STAT        BIT5\r
-#define ISP1761_DC_INTERRUPT_DMA            BIT6\r
-#define ISP1761_DC_INTERRUPT_VBUS           BIT7\r
-#define ISP1761_DC_INTERRUPT_EP0SETUP       BIT8\r
-#define ISP1761_DC_INTERRUPT_EP0RX          BIT10\r
-#define ISP1761_DC_INTERRUPT_EP0TX          BIT11\r
-#define ISP1761_DC_INTERRUPT_EP1RX          BIT12\r
-#define ISP1761_DC_INTERRUPT_EP1TX          BIT13\r
-// All valid peripheral controller interrupts\r
-#define ISP1761_DC_INTERRUPT_MASK           0x003FFFDFF\r
-\r
-#define ISP1761_ADDRESS                     0x200\r
-#define ISP1761_ADDRESS_DEVEN               BIT7\r
-\r
-#define ISP1761_MODE                        0x20C\r
-#define ISP1761_MODE_DATA_BUS_WIDTH         BIT8\r
-#define ISP1761_MODE_CLKAON                 BIT7\r
-#define ISP1761_MODE_SFRESET                BIT4\r
-#define ISP1761_MODE_WKUPCS                 BIT2\r
-\r
-#define ISP1761_ENDPOINT_MAX_PACKET_SIZE    0x204\r
-\r
-#define ISP1761_ENDPOINT_TYPE               0x208\r
-#define ISP1761_ENDPOINT_TYPE_NOEMPKT       BIT4\r
-#define ISP1761_ENDPOINT_TYPE_ENABLE        BIT3\r
-\r
-#define ISP1761_INTERRUPT_CONFIG            0x210\r
-// Interrupt config value to only interrupt on ACK of IN and OUT tokens\r
-#define ISP1761_INTERRUPT_CONFIG_ACK_ONLY   BIT2 | BIT5 | BIT6\r
-\r
-#define ISP1761_DC_INTERRUPT                0x218\r
-#define ISP1761_DC_INTERRUPT_ENABLE         0x214\r
-\r
-#define ISP1761_CTRL_FUNCTION               0x228\r
-#define ISP1761_CTRL_FUNCTION_VENDP         BIT3\r
-#define ISP1761_CTRL_FUNCTION_DSEN          BIT2\r
-#define ISP1761_CTRL_FUNCTION_STATUS        BIT1\r
-\r
-#define ISP1761_DEVICE_UNLOCK               0x27C\r
-#define ISP1761_DEVICE_UNLOCK_MAGIC         0xAA37\r
-\r
-#define ISP1761_SW_RESET_REG                0x30C\r
-#define ISP1761_SW_RESET_ALL                BIT0\r
-\r
-#define ISP1761_DEVICE_ID                   0x370\r
-\r
-#define ISP1761_OTG_CTRL_SET                0x374\r
-#define ISP1761_OTG_CTRL_CLR                OTG_CTRL_SET + 2\r
-#define ISP1761_OTG_CTRL_OTG_DISABLE        BIT10\r
-#define ISP1761_OTG_CTRL_VBUS_CHRG          BIT6\r
-#define ISP1761_OTG_CTRL_VBUS_DISCHRG       BIT5\r
-#define ISP1761_OTG_CTRL_DM_PULLDOWN        BIT2\r
-#define ISP1761_OTG_CTRL_DP_PULLDOWN        BIT1\r
-#define ISP1761_OTG_CTRL_DP_PULLUP          BIT0\r
-\r
-#define ISP1761_OTG_STATUS                  0x378\r
-#define ISP1761_OTG_STATUS_B_SESS_END       BIT7\r
-#define ISP1761_OTG_STATUS_A_B_SESS_VLD     BIT1\r
-\r
-#define ISP1761_OTG_INTERRUPT_LATCH_SET     0x37C\r
-#define ISP1761_OTG_INTERRUPT_LATCH_CLR     0x37E\r
-#define ISP1761_OTG_INTERRUPT_ENABLE_RISE   0x384\r
-\r
-#define ISP1761_DMA_ENDPOINT_INDEX          0x258\r
-\r
-#define ISP1761_ENDPOINT_INDEX              0x22c\r
-#define ISP1761_DATA_PORT                   0x220\r
-#define ISP1761_BUFFER_LENGTH               0x21c\r
-\r
-// Device ID Values\r
-#define PHILLIPS_VENDOR_ID_VAL 0x04cc\r
-#define ISP1761_PRODUCT_ID_VAL 0x1761\r
-#define ISP1761_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\\r
-                               PHILLIPS_VENDOR_ID_VAL)\r
-\r
-#endif //ifndef __ISP1761_USB_DXE_H__\r