+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#include "Lan9118Dxe.h"\r
-\r
-STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };\r
-\r
-/**\r
- This internal function reverses bits for 32bit data.\r
-\r
- @param Value The data to be reversed.\r
-\r
- @return Data reversed.\r
-\r
-**/\r
-UINT32\r
-ReverseBits (\r
- UINT32 Value\r
- )\r
-{\r
- UINTN Index;\r
- UINT32 NewValue;\r
-\r
- NewValue = 0;\r
- for (Index = 0; Index < 32; Index++) {\r
- if ((Value & (1 << Index)) != 0) {\r
- NewValue = NewValue | (1 << (31 - Index));\r
- }\r
- }\r
-\r
- return NewValue;\r
-}\r
-\r
-/*\r
-** Create Ethernet CRC\r
-**\r
-** INFO USED:\r
-** 1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check\r
-**\r
-** 2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html\r
-**\r
-** 3: http://en.wikipedia.org/wiki/Computation_of_CRC\r
-*/\r
-UINT32\r
-GenEtherCrc32 (\r
- IN EFI_MAC_ADDRESS *Mac,\r
- IN UINT32 AddrLen\r
- )\r
-{\r
- INT32 Iter;\r
- UINT32 Remainder;\r
- UINT8 *Ptr;\r
-\r
- Iter = 0;\r
- Remainder = 0xFFFFFFFF; // 0xFFFFFFFF is standard seed for Ethernet\r
-\r
- // Convert Mac Address to array of bytes\r
- Ptr = (UINT8*)Mac;\r
-\r
- // Generate the Crc bit-by-bit (LSB first)\r
- while (AddrLen--) {\r
- Remainder ^= *Ptr++;\r
- for (Iter = 0;Iter < 8;Iter++) {\r
- // Check if exponent is set\r
- if (Remainder & 1) {\r
- Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;\r
- } else {\r
- Remainder = (Remainder >> 1) ^ 0;\r
- }\r
- }\r
- }\r
-\r
- // Reverse the bits before returning (to Big Endian)\r
- //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())\r
- return ReverseBits (Remainder);\r
-}\r
-\r
-// Function to read from MAC indirect registers\r
-UINT32\r
-IndirectMACRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 MacCSR;\r
-\r
- // Check index is in the range\r
- ASSERT(Index <= 12);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Set CSR busy bit to ensure read will occur\r
- // Set the R/W bit to indicate we are reading\r
- // Set the index of CSR Address to access desired register\r
- MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r
-\r
- // Write to the register\r
- Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Now read from data register to get read value\r
- return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA);\r
-}\r
-\r
-/*\r
- * LAN9118 chips have special restrictions on some back-to-back Write/Read or\r
- * Read/Read pairs of accesses. After a read or write that changes the state of\r
- * the device, there is a period in which stale values may be returned in\r
- * response to a read. This period is dependent on the registers accessed.\r
- *\r
- * We must delay prior reads by this period. This can either be achieved by\r
- * timer-based delays, or by performing dummy reads of the BYTE_TEST register,\r
- * for which the recommended number of reads is described in the LAN9118 data\r
- * sheet. This is required in addition to any memory barriers.\r
- *\r
- * This function performs a number of dummy reads of the BYTE_TEST register, as\r
- * a building block for the above.\r
- */\r
-VOID\r
-WaitDummyReads (\r
- UINTN Count\r
- )\r
-{\r
- while (Count--)\r
- MmioRead32(LAN9118_BYTE_TEST);\r
-}\r
-\r
-UINT32\r
-Lan9118RawMmioRead32(\r
- UINTN Address,\r
- UINTN Delay\r
- )\r
-{\r
- UINT32 Value;\r
-\r
- Value = MmioRead32(Address);\r
- WaitDummyReads(Delay);\r
- return Value;\r
-}\r
-\r
-UINT32\r
-Lan9118RawMmioWrite32(\r
- UINTN Address,\r
- UINT32 Value,\r
- UINTN Delay\r
- )\r
-{\r
- MmioWrite32(Address, Value);\r
- WaitDummyReads(Delay);\r
- return Value;\r
-}\r
-\r
-// Function to write to MAC indirect registers\r
-UINT32\r
-IndirectMACWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 ValueWritten;\r
- UINT32 MacCSR;\r
-\r
- // Check index is in the range\r
- ASSERT(Index <= 12);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Set CSR busy bit to ensure read will occur\r
- // Set the R/W bit to indicate we are writing\r
- // Set the index of CSR Address to access desired register\r
- MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r
-\r
- // Now write the value to the register before issuing the write command\r
- ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
-\r
- // Write the config to the register\r
- Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-// Function to read from MII register (PHY Access)\r
-UINT32\r
-IndirectPHYRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 ValueRead;\r
- UINT32 MiiAcc;\r
-\r
- // Check it is a valid index\r
- ASSERT(Index < 31);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Clear the R/W bit to indicate we are reading\r
- // Set the index of the MII register\r
- // Set the PHY Address\r
- // Set the MII busy bit to allow read\r
- MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
-\r
- // Now write this config to register\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Now read the value of the register\r
- ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register\r
-\r
- return ValueRead;\r
-}\r
-\r
-\r
-// Function to write to the MII register (PHY Access)\r
-UINT32\r
-IndirectPHYWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 MiiAcc;\r
- UINT32 ValueWritten;\r
-\r
- // Check it is a valid index\r
- ASSERT(Index < 31);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Clear the R/W bit to indicate we are reading\r
- // Set the index of the MII register\r
- // Set the PHY Address\r
- // Set the MII busy bit to allow read\r
- MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
-\r
- // Write the desired value to the register first\r
- ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));\r
-\r
- // Now write the config to register\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
-\r
- // Wait for operation to terminate\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-\r
-/* ---------------- EEPROM Operations ------------------ */\r
-\r
-\r
-// Function to read from EEPROM memory\r
-UINT32\r
-IndirectEEPROMRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 EepromCmd;\r
-\r
- // Set the busy bit to ensure read will occur\r
- EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;\r
-\r
- // Set the index to access desired EEPROM memory location\r
- EepromCmd |= E2P_EPC_ADDRESS(Index);\r
-\r
- // Write to Eeprom command register\r
- Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Check that operation didn't time out\r
- if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r
- return 0;\r
- }\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Finally read the value\r
- return Lan9118MmioRead32 (LAN9118_E2P_DATA);\r
-}\r
-\r
-// Function to write to EEPROM memory\r
-UINT32\r
-IndirectEEPROMWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 ValueWritten;\r
- UINT32 EepromCmd;\r
-\r
- ValueWritten = 0;\r
-\r
- // Read the EEPROM Command register\r
- EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD);\r
-\r
- // Set the busy bit to ensure read will occur\r
- EepromCmd |= ((UINT32)1 << 31);\r
-\r
- // Set the EEPROM command to write(0b011)\r
- EepromCmd &= ~(7 << 28); // Clear the command first\r
- EepromCmd |= (3 << 28); // Write 011\r
-\r
- // Set the index to access desired EEPROM memory location\r
- EepromCmd |= (Index & 0xF);\r
-\r
- // Write the value to the data register first\r
- ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value);\r
-\r
- // Write to Eeprom command register\r
- Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Check that operation didn't time out\r
- if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r
- return 0;\r
- }\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-/* ---------------- General Operations ----------------- */\r
-\r
-VOID\r
-Lan9118SetMacAddress (\r
- EFI_MAC_ADDRESS *Mac,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,\r
- (Mac->Addr[0] & 0xFF) |\r
- ((Mac->Addr[1] & 0xFF) << 8) |\r
- ((Mac->Addr[2] & 0xFF) << 16) |\r
- ((Mac->Addr[3] & 0xFF) << 24)\r
- );\r
-\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,\r
- (UINT32)(Mac->Addr[4] & 0xFF) |\r
- ((Mac->Addr[5] & 0xFF) << 8)\r
- );\r
-}\r
-\r
-VOID\r
-Lan9118ReadMacAddress (\r
- OUT EFI_MAC_ADDRESS *MacAddress\r
- )\r
-{\r
- UINT32 MacAddrHighValue;\r
- UINT32 MacAddrLowValue;\r
-\r
- // Read the Mac Addr high register\r
- MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);\r
- // Read the Mac Addr low register\r
- MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);\r
-\r
- SetMem (MacAddress, sizeof(*MacAddress), 0);\r
- MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);\r
- MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;\r
- MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;\r
- MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;\r
- MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);\r
- MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;\r
-}\r
-\r
-/*\r
- * Power up the 9118 and find its MAC address.\r
- *\r
- * This operation can be carried out when the LAN9118 is in any power state\r
- *\r
- */\r
-EFI_STATUS\r
-Lan9118Initialize (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINTN Retries;\r
- UINT64 DefaultMacAddress;\r
-\r
- // Attempt to wake-up the device if it is in a lower power state\r
- if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
- DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
- Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
- }\r
-\r
- // Check that device is active\r
- Retries = 20;\r
- while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- if (!Retries) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- Retries = 20;\r
- while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- if (!Retries) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- // Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r
- // current address.\r
- if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
- DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r
-\r
- // If we had an address before (set by StationAddress), continue to use it\r
- if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {\r
- Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);\r
- } else {\r
- // If there are no cached addresses, then fall back to a default\r
- DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r
- DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r
- Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r
- CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r
- }\r
- } else {\r
- // Store the MAC address that was loaded from EEPROM\r
- Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);\r
- CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);\r
- }\r
-\r
- // Clear and acknowledge interrupts\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
-\r
- // Do self tests here?\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Perform software reset on the LAN9118\r
-// Return 0 on success, -1 on error\r
-EFI_STATUS\r
-SoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 HwConf;\r
- UINT32 ResetTime;\r
-\r
- // Initialize variable\r
- ResetTime = 0;\r
-\r
- // Stop Rx and Tx\r
- StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);\r
- StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r
-\r
- // Issue the reset\r
- HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
- HwConf |= 1;\r
-\r
- // Set the Must Be One (MBO) bit\r
- if (((HwConf & HWCFG_MBO) >> 20) == 0) {\r
- HwConf |= HWCFG_MBO;\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Write the configuration\r
- Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
-\r
- // Wait for reset to complete\r
- while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
-\r
- gBS->Stall (LAN9118_STALL);\r
- ResetTime += 1;\r
-\r
- // If time taken exceeds 100us, then there was an error condition\r
- if (ResetTime > 1000) {\r
- Snp->Mode->State = EfiSimpleNetworkStopped;\r
- return EFI_TIMEOUT;\r
- }\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // TODO we probably need to re-set the mac address here.\r
-\r
- // Clear and acknowledge all interrupts\r
- if (Flags & SOFT_RESET_CLEAR_INT) {\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
- }\r
-\r
- // Do self tests here?\r
- if (Flags & SOFT_RESET_SELF_TEST) {\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Perform PHY software reset\r
-EFI_STATUS\r
-PhySoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 PmtCtrl = 0;\r
-\r
- // PMT PHY reset takes precedence over BCR\r
- if (Flags & PHY_RESET_PMT) {\r
- PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
- PmtCtrl |= MPTCTRL_PHY_RST;\r
- Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
-\r
- // Wait for completion\r
- while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- // PHY Basic Control Register reset\r
- } else if (Flags & PHY_RESET_BCR) {\r
- IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r
-\r
- // Wait for completion\r
- while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- }\r
-\r
- // Clear and acknowledge all interrupts\r
- if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Configure hardware for LAN9118\r
-EFI_STATUS\r
-ConfigureHardware (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 GpioConf;\r
-\r
- // Check if we want to use LEDs on GPIO\r
- if (Flags & HW_CONF_USE_LEDS) {\r
- GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG);\r
-\r
- // Enable GPIO as LEDs and Config as Push-Pull driver\r
- GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r
- GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r
-\r
- // Write the configuration\r
- Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Configure flow control\r
-EFI_STATUS\r
-ConfigureFlow (\r
- UINT32 Flags,\r
- UINT32 HighTrig,\r
- UINT32 LowTrig,\r
- UINT32 BPDuration,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Do auto-negotiation\r
-EFI_STATUS\r
-AutoNegotiate (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 PhyControl;\r
- UINT32 PhyStatus;\r
- UINT32 Features;\r
- UINT32 Retries;\r
-\r
- // First check that auto-negotiation is supported\r
- PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
- if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {\r
- DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Check that link is up first\r
- if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r
- // Wait until it is up or until Time Out\r
- Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r
- while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
- gBS->Stall (LAN9118_STALL);\r
- Retries--;\r
- if (!Retries) {\r
- DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));\r
- return EFI_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- // Configure features to advertise\r
- Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);\r
-\r
- if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {\r
- // Link speed capabilities\r
- Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);\r
-\r
- // Pause frame capabilities\r
- Features &= ~(PHYANA_PAUSE_OP_MASK);\r
- Features |= 3 << 10;\r
- }\r
- Features &= FixedPcdGet32 (PcdLan9118NegotiationFeatureMask);\r
-\r
- // Write the features\r
- IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);\r
-\r
- // Read control register\r
- PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);\r
-\r
- // Enable Auto-Negotiation\r
- if ((PhyControl & PHYCR_AUTO_EN) == 0) {\r
- PhyControl |= PHYCR_AUTO_EN;\r
- }\r
-\r
- // Restart auto-negotiation\r
- PhyControl |= PHYCR_RST_AUTO;\r
-\r
- // Enable collision test if required to do so\r
- if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {\r
- PhyControl |= PHYCR_COLL_TEST;\r
- } else {\r
- PhyControl &= ~ PHYCR_COLL_TEST;\r
- }\r
-\r
- // Write this configuration\r
- IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);\r
-\r
- // Wait until process has completed\r
- while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Check the Link Status and take appropriate action\r
-EFI_STATUS\r
-CheckLinkStatus (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- // Get the PHY Status\r
- UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
-\r
- if (PhyBStatus & PHYSTS_LINK_STS) {\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_DEVICE_ERROR;\r
- }\r
-}\r
-\r
-// Stop the transmitter\r
-EFI_STATUS\r
-StopTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 TxCfg;\r
-\r
- MacCsr = 0;\r
- TxCfg = 0;\r
-\r
- // Check if we want to clear tx\r
- if (Flags & STOP_TX_CLEAR) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
-\r
- // Check if already stopped\r
- if (Flags & STOP_TX_MAC) {\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if (MacCsr & MACCR_TX_EN) {\r
- MacCsr &= ~MACCR_TX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
- }\r
-\r
- if (Flags & STOP_TX_CFG) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
-\r
- if (TxCfg & TXCFG_TX_ON) {\r
- TxCfg |= TXCFG_STOP_TX;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
-\r
- // Wait for Tx to finish transmitting\r
- while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Stop the receiver\r
-EFI_STATUS\r
-StopRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 RxCfg;\r
-\r
- RxCfg = 0;\r
-\r
- // Check if already stopped\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if (MacCsr & MACCR_RX_EN) {\r
- MacCsr &= ~ MACCR_RX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
-\r
- // Check if we want to clear receiver FIFOs\r
- if (Flags & STOP_RX_CLEAR) {\r
- RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
- RxCfg |= RXCFG_RX_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
-\r
- while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Start the transmitter\r
-EFI_STATUS\r
-StartTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 TxCfg;\r
-\r
- MacCsr = 0;\r
- TxCfg = 0;\r
-\r
- // Check if we want to clear tx\r
- if (Flags & START_TX_CLEAR) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
-\r
- // Check if tx was started from MAC and enable if not\r
- if (Flags & START_TX_MAC) {\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- if ((MacCsr & MACCR_TX_EN) == 0) {\r
- MacCsr |= MACCR_TX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
- }\r
-\r
- // Check if tx was started from TX_CFG and enable if not\r
- if (Flags & START_TX_CFG) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- if ((TxCfg & TXCFG_TX_ON) == 0) {\r
- TxCfg |= TXCFG_TX_ON;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
- }\r
-\r
- // Set the tx data trigger level\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Start the receiver\r
-EFI_STATUS\r
-StartRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 RxCfg;\r
-\r
- RxCfg = 0;\r
-\r
- // Check if already started\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if ((MacCsr & MACCR_RX_EN) == 0) {\r
- // Check if we want to clear receiver FIFOs before starting\r
- if (Flags & START_RX_CLEAR) {\r
- RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
- RxCfg |= RXCFG_RX_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
-\r
- while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
- }\r
-\r
- MacCsr |= MACCR_RX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Check Tx Data available space\r
-UINT32\r
-TxDataFreeSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 TxInf;\r
- UINT32 FreeSpace;\r
-\r
- // Get the amount of free space from information register\r
- TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
- FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r
-\r
- return FreeSpace; // Value in bytes\r
-}\r
-\r
-// Check Tx Status used space\r
-UINT32\r
-TxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 TxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
- UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r
-\r
- return UsedSpace << 2; // Value in bytes\r
-}\r
-\r
-// Check Rx Data used space\r
-UINT32\r
-RxDataUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 RxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
- UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r
-\r
- return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r
-}\r
-\r
-// Check Rx Status used space\r
-UINT32\r
-RxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 RxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
- UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r
-\r
- return UsedSpace << 2; // Value in bytes\r
-}\r
-\r
-\r
-// Change the allocation of FIFOs\r
-EFI_STATUS\r
-ChangeFifoAllocation (\r
- IN UINT32 Flags,\r
- IN OUT UINTN *TxDataSize OPTIONAL,\r
- IN OUT UINTN *RxDataSize OPTIONAL,\r
- IN OUT UINT32 *TxStatusSize OPTIONAL,\r
- IN OUT UINT32 *RxStatusSize OPTIONAL,\r
- IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 HwConf;\r
- UINT32 TxFifoOption;\r
-\r
- // Check that desired sizes don't exceed limits\r
- if (*TxDataSize > TX_FIFO_MAX_SIZE)\r
- return EFI_INVALID_PARAMETER;\r
-\r
-#if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)\r
- if (*RxDataSize > RX_FIFO_MAX_SIZE) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-#endif\r
-\r
- if (Flags & ALLOC_USE_DEFAULT) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- // If we use the FIFOs (always use this first)\r
- if (Flags & ALLOC_USE_FIFOS) {\r
- // Read the current value of allocation\r
- HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
- TxFifoOption = (HwConf >> 16) & 0xF;\r
-\r
- // Choose the correct size (always use larger than requested if possible)\r
- if (*TxDataSize < TX_FIFO_MIN_SIZE) {\r
- *TxDataSize = TX_FIFO_MIN_SIZE;\r
- *RxDataSize = 13440;\r
- *RxStatusSize = 896;\r
- TxFifoOption = 2;\r
- } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {\r
- *TxDataSize = 2560;\r
- *RxDataSize = 12480;\r
- *RxStatusSize = 832;\r
- TxFifoOption = 3;\r
- } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {\r
- *TxDataSize = 3584;\r
- *RxDataSize = 11520;\r
- *RxStatusSize = 768;\r
- TxFifoOption = 4;\r
- } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option\r
- *TxDataSize = 4608;\r
- *RxDataSize = 10560;\r
- *RxStatusSize = 704;\r
- TxFifoOption = 5;\r
- } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {\r
- *TxDataSize = 5632;\r
- *RxDataSize = 9600;\r
- *RxStatusSize = 640;\r
- TxFifoOption = 6;\r
- } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {\r
- *TxDataSize = 6656;\r
- *RxDataSize = 8640;\r
- *RxStatusSize = 576;\r
- TxFifoOption = 7;\r
- } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {\r
- *TxDataSize = 7680;\r
- *RxDataSize = 7680;\r
- *RxStatusSize = 512;\r
- TxFifoOption = 8;\r
- } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {\r
- *TxDataSize = 8704;\r
- *RxDataSize = 6720;\r
- *RxStatusSize = 448;\r
- TxFifoOption = 9;\r
- } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {\r
- *TxDataSize = 9728;\r
- *RxDataSize = 5760;\r
- *RxStatusSize = 384;\r
- TxFifoOption = 10;\r
- } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {\r
- *TxDataSize = 10752;\r
- *RxDataSize = 4800;\r
- *RxStatusSize = 320;\r
- TxFifoOption = 11;\r
- } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {\r
- *TxDataSize = 11776;\r
- *RxDataSize = 3840;\r
- *RxStatusSize = 256;\r
- TxFifoOption = 12;\r
- } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {\r
- *TxDataSize = 12800;\r
- *RxDataSize = 2880;\r
- *RxStatusSize = 192;\r
- TxFifoOption = 13;\r
- } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {\r
- *TxDataSize = 13824;\r
- *RxDataSize = 1920;\r
- *RxStatusSize = 128;\r
- TxFifoOption = 14;\r
- }\r
- } else {\r
- ASSERT(0); // Untested code path\r
- HwConf = 0;\r
- TxFifoOption = 0;\r
- }\r
-\r
- // Do we need DMA?\r
- if (Flags & ALLOC_USE_DMA) {\r
- return EFI_UNSUPPORTED; // Unsupported as of now\r
- }\r
- // Clear and assign the new size option\r
- HwConf &= ~(0xF0000);\r
- HwConf |= ((TxFifoOption & 0xF) << 16);\r
- Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
-\r
- return EFI_SUCCESS;\r
-}\r
projects / mirror_edk2.git / blobdiff