+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#include "Lan9118Dxe.h"\r
-\r
-typedef struct {\r
- MAC_ADDR_DEVICE_PATH Lan9118;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} LAN9118_DEVICE_PATH;\r
-\r
-LAN9118_DEVICE_PATH Lan9118PathTemplate = {\r
- {\r
- {\r
- MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP,\r
- { (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)), (UINT8) ((sizeof(MAC_ADDR_DEVICE_PATH)) >> 8) }\r
- },\r
- { { 0 } },\r
- 0\r
- },\r
- {\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 }\r
- }\r
-};\r
-\r
-/*\r
-** Entry point for the LAN9118 driver\r
-**\r
-*/\r
-EFI_STATUS\r
-EFIAPI\r
-Lan9118DxeEntry (\r
- IN EFI_HANDLE Handle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- LAN9118_DRIVER *LanDriver;\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp;\r
- EFI_SIMPLE_NETWORK_MODE *SnpMode;\r
- LAN9118_DEVICE_PATH *Lan9118Path;\r
- EFI_HANDLE ControllerHandle;\r
-\r
- // The PcdLan9118DxeBaseAddress PCD must be defined\r
- ASSERT (PcdGet32 (PcdLan9118DxeBaseAddress) != 0);\r
-\r
- // Allocate Resources\r
- LanDriver = AllocateZeroPool (sizeof (LAN9118_DRIVER));\r
- if (LanDriver == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- Lan9118Path = (LAN9118_DEVICE_PATH*)AllocateCopyPool (sizeof (LAN9118_DEVICE_PATH), &Lan9118PathTemplate);\r
- if (Lan9118Path == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- // Initialize pointers\r
- Snp = &(LanDriver->Snp);\r
- SnpMode = &(LanDriver->SnpMode);\r
- Snp->Mode = SnpMode;\r
-\r
- // Set the signature of the LAN Driver structure\r
- LanDriver->Signature = LAN9118_SIGNATURE;\r
-\r
- // Assign fields and func pointers\r
- Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;\r
- Snp->WaitForPacket = NULL;\r
- Snp->Initialize = SnpInitialize;\r
- Snp->Start = SnpStart;\r
- Snp->Stop = SnpStop;\r
- Snp->Reset = SnpReset;\r
- Snp->Shutdown = SnpShutdown;\r
- Snp->ReceiveFilters = SnpReceiveFilters;\r
- Snp->StationAddress = SnpStationAddress;\r
- Snp->Statistics = SnpStatistics;\r
- Snp->MCastIpToMac = SnpMcastIptoMac;\r
- Snp->NvData = SnpNvData;\r
- Snp->GetStatus = SnpGetStatus;\r
- Snp->Transmit = SnpTransmit;\r
- Snp->Receive = SnpReceive;\r
-\r
- // Start completing simple network mode structure\r
- SnpMode->State = EfiSimpleNetworkStopped;\r
- SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN; // HW address is 6 bytes\r
- SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD); // Not sure of this\r
- SnpMode->MaxPacketSize = EFI_PAGE_SIZE; // Preamble + SOF + Ether Frame (with VLAN tag +4bytes)\r
- SnpMode->NvRamSize = 0; // No NVRAM with this device\r
- SnpMode->NvRamAccessSize = 0; // No NVRAM with this device\r
-\r
- //\r
- // Claim that all receive filter settings are supported, though the MULTICAST mode\r
- // is not completely supported. The LAN9118 Ethernet controller is only able to\r
- // do a "hash filtering" and not a perfect filtering on multicast addresses. The\r
- // controller does not filter the multicast addresses directly but a hash value\r
- // of them. The hash value of a multicast address is derived from its CRC and\r
- // ranges from 0 to 63 included.\r
- // We claim that the perfect MULTICAST filtering mode is supported because\r
- // we do not want the user to switch directly to the PROMISCOUS_MULTICAST mode\r
- // and thus not being able to take advantage of the hash filtering.\r
- //\r
- SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |\r
- EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |\r
- EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |\r
- EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |\r
- EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;\r
-\r
- // We do not intend to receive anything for the time being.\r
- SnpMode->ReceiveFilterSetting = 0;\r
-\r
- // LAN9118 has 64bit hash table, can filter 64 MCast MAC Addresses\r
- SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;\r
- SnpMode->MCastFilterCount = 0;\r
- ZeroMem (&SnpMode->MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));\r
-\r
- // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)\r
- SnpMode->IfType = NET_IFTYPE_ETHERNET;\r
-\r
- // Mac address is changeable as it is loaded from erasable memory\r
- SnpMode->MacAddressChangeable = TRUE;\r
-\r
- // Can only transmit one packet at a time\r
- SnpMode->MultipleTxSupported = FALSE;\r
-\r
- // MediaPresent checks for cable connection and partner link\r
- SnpMode->MediaPresentSupported = TRUE;\r
- SnpMode->MediaPresent = FALSE;\r
-\r
- // Set broadcast address\r
- SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);\r
-\r
- // Power up the device so we can find the MAC address\r
- Status = Lan9118Initialize (Snp);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "LAN9118: Error initialising hardware\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Assign fields for device path\r
- CopyMem (&Lan9118Path->Lan9118.MacAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);\r
- Lan9118Path->Lan9118.IfType = Snp->Mode->IfType;\r
-\r
- // Initialise the protocol\r
- ControllerHandle = NULL;\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &ControllerHandle,\r
- &gEfiSimpleNetworkProtocolGuid, Snp,\r
- &gEfiDevicePathProtocolGuid, Lan9118Path,\r
- NULL\r
- );\r
- // Say what the status of loading the protocol structure is\r
- if (EFI_ERROR(Status)) {\r
- FreePool (LanDriver);\r
- } else {\r
- LanDriver->ControllerHandle = ControllerHandle;\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/*\r
- * UEFI Start() function\r
- *\r
- * Parameters:\r
- *\r
- * @param Snp: A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.\r
- *\r
- * Description:\r
- *\r
- * This function starts a network interface. If the network interface successfully starts, then\r
- * EFI_SUCCESS will be returned.\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStart (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- // Check Snp instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check state\r
- if ((Snp->Mode->State == EfiSimpleNetworkStarted) ||\r
- (Snp->Mode->State == EfiSimpleNetworkInitialized) ) {\r
- return EFI_ALREADY_STARTED;\r
- }\r
-\r
- // Change state\r
- Snp->Mode->State = EfiSimpleNetworkStarted;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- * UEFI Stop() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStop (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp\r
- )\r
-{\r
- // Check Snp Instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check state of the driver\r
- if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Stop the Tx and Rx\r
- StopTx (STOP_TX_CFG | STOP_TX_MAC, Snp);\r
- StopRx (0, Snp);\r
-\r
- // Change the state\r
- switch (Snp->Mode->State) {\r
- case EfiSimpleNetworkStarted:\r
- case EfiSimpleNetworkInitialized:\r
- Snp->Mode->State = EfiSimpleNetworkStopped;\r
- break;\r
- default:\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Put the device into a power saving mode ?\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Allocated receive and transmit buffers\r
-STATIC UINT32 gTxBuffer = 0;\r
-\r
-/*\r
- * UEFI Initialize() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpInitialize (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN UINTN RxBufferSize OPTIONAL,\r
- IN UINTN TxBufferSize OPTIONAL\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT32 PmConf;\r
- INT32 AllocResult;\r
- UINT32 RxStatusSize;\r
- UINT32 TxStatusSize;\r
-\r
- // Initialize variables\r
- // Global variables to hold tx and rx FIFO allocation\r
- gTxBuffer = 0;\r
-\r
- // Check Snp Instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // First check that driver has not already been initialized\r
- if (Snp->Mode->State == EfiSimpleNetworkInitialized) {\r
- DEBUG ((EFI_D_WARN, "LAN9118 Driver already initialized\n"));\r
- return EFI_SUCCESS;\r
- } else\r
- if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "LAN9118 Driver not started\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Initiate a PHY reset\r
- Status = PhySoftReset (PHY_RESET_PMT, Snp);\r
- if (EFI_ERROR (Status)) {\r
- Snp->Mode->State = EfiSimpleNetworkStopped;\r
- DEBUG ((EFI_D_WARN, "Warning: Link not ready after TimeOut. Check ethernet cable\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Initiate a software reset\r
- Status = SoftReset (0, Snp);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG ((EFI_D_WARN, "Soft Reset Failed: Hardware Error\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Read the PM register\r
- PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
-\r
- // MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets\r
- // MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode\r
- // MPTCTRL_PME_EN: Allow Power Management Events\r
- PmConf = 0;\r
- PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN);\r
-\r
- // Write the current configuration to the register\r
- Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
-\r
- // Configure GPIO and HW\r
- Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Assign the transmitter buffer size (default values)\r
- TxStatusSize = LAN9118_TX_STATUS_SIZE;\r
- RxStatusSize = LAN9118_RX_STATUS_SIZE;\r
-\r
- // Check that a buff size was specified\r
- if (TxBufferSize > 0) {\r
- if (RxBufferSize == 0) {\r
- RxBufferSize = LAN9118_RX_DATA_SIZE;\r
- }\r
-\r
- AllocResult = ChangeFifoAllocation (\r
- ALLOC_USE_FIFOS,\r
- &TxBufferSize,\r
- &RxBufferSize,\r
- &TxStatusSize,\r
- &RxStatusSize,\r
- Snp\r
- );\r
-\r
- if (AllocResult < 0) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- }\r
-\r
- // Do auto-negotiation if supported\r
- Status = AutoNegotiate (AUTO_NEGOTIATE_ADVERTISE_ALL, Snp);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG ((EFI_D_WARN, "LAN9118: Auto Negotiation failed.\n"));\r
- }\r
-\r
- // Configure flow control depending on speed capabilities\r
- Status = ConfigureFlow (0, 0, 0, 0, Snp);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Enable the transmitter\r
- Status = StartTx (START_TX_MAC | START_TX_CFG, Snp);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Now acknowledge all interrupts\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, ~0);\r
-\r
- // Declare the driver as initialized\r
- Snp->Mode->State = EfiSimpleNetworkInitialized;\r
-\r
- return Status;\r
-}\r
-\r
-/*\r
- * UEFI Reset () function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReset (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN Verification\r
- )\r
-{\r
- UINT32 PmConf;\r
- UINT32 HwConf;\r
- UINT32 ResetFlags;\r
- EFI_STATUS Status;\r
-\r
- PmConf = 0;\r
- HwConf = 0;\r
- ResetFlags = 0;\r
-\r
- // Check Snp Instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // First check that driver has not already been initialized\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not yet initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not started\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Initiate a PHY reset\r
- Status = PhySoftReset (PHY_RESET_PMT, Snp);\r
- if (EFI_ERROR (Status)) {\r
- Snp->Mode->State = EfiSimpleNetworkStopped;\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Initiate a software reset\r
- ResetFlags |= SOFT_RESET_CHECK_MAC_ADDR_LOAD | SOFT_RESET_CLEAR_INT;\r
-\r
- if (Verification) {\r
- ResetFlags |= SOFT_RESET_SELF_TEST;\r
- }\r
-\r
- Status = SoftReset (ResetFlags, Snp);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_WARN, "Warning: Soft Reset Failed: Hardware Error\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Read the PM register\r
- PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
-\r
- // MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets\r
- // MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode\r
- // MPTCTRL_PME_EN: Allow Power Management Events\r
- PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN);\r
-\r
- // Write the current configuration to the register\r
- Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
-\r
- // Reactivate the LEDs\r
- Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Check that a buffer size was specified in SnpInitialize\r
- if (gTxBuffer != 0) {\r
- HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register\r
- HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first\r
- HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize\r
-\r
- Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf\r
- }\r
-\r
- // Enable the receiver and transmitter and clear their contents\r
- StartRx (START_RX_CLEAR, Snp);\r
- StartTx (START_TX_MAC | START_TX_CFG | START_TX_CLEAR, Snp);\r
-\r
- // Now acknowledge all interrupts\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, ~0);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- * UEFI Shutdown () function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpShutdown (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- // Check Snp Instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // First check that driver has not already been initialized\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not yet initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not started\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Initiate a PHY reset\r
- Status = PhySoftReset (PHY_RESET_PMT, Snp);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Initiate a software reset\r
- Status = SoftReset (0, Snp);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_WARN, "Warning: Soft Reset Failed: Hardware Error\n"));\r
- return Status;\r
- }\r
-\r
- // Back to the started and thus not initialized state\r
- Snp->Mode->State = EfiSimpleNetworkStarted;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Enable and/or disable the receive filters of the LAN9118\r
-\r
- Please refer to the UEFI specification for the precedence rules among the\r
- Enable, Disable and ResetMCastFilter parameters.\r
-\r
- @param[in] Snp A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL\r
- instance.\r
- @param[in] Enable A bit mask of receive filters to enable.\r
- @param[in] Disable A bit mask of receive filters to disable.\r
- @param[in] ResetMCastFilter Set to TRUE to reset the contents of the multicast\r
- receive filters on the network interface to\r
- their default values.\r
- @param[in] MCastFilterCnt Number of multicast HW MAC addresses in the new\r
- MCastFilter list. This value must be less than or\r
- equal to the MCastFilterCnt field of\r
- EFI_SIMPLE_NETWORK_MODE. This field is optional if\r
- ResetMCastFilter is TRUE.\r
- @param[in] MCastFilter A pointer to a list of new multicast receive\r
- filter HW MAC addresses. This list will replace\r
- any existing multicast HW MAC address list. This\r
- field is optional if ResetMCastFilter is TRUE.\r
-\r
- @retval EFI_SUCCESS The receive filters of the LAN9118 were updated.\r
- @retval EFI_NOT_STARTED The LAN9118 has not been started.\r
- @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE :\r
- . This is NULL\r
- . Multicast is being enabled (the\r
- EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is set in\r
- Enable, it is not set in Disable, and ResetMCastFilter\r
- is FALSE) and MCastFilterCount is zero.\r
- . Multicast is being enabled and MCastFilterCount is\r
- greater than Snp->Mode->MaxMCastFilterCount.\r
- . Multicast is being enabled and MCastFilter is NULL\r
- . Multicast is being enabled and one or more of the\r
- addresses in the MCastFilter list are not valid\r
- multicast MAC addresses.\r
- @retval EFI_DEVICE_ERROR The LAN9118 has been started but not initialized.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReceiveFilters (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,\r
- IN UINT32 Enable,\r
- IN UINT32 Disable,\r
- IN BOOLEAN ResetMCastFilter,\r
- IN UINTN MCastFilterCnt OPTIONAL,\r
- IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL\r
- )\r
-{\r
- EFI_SIMPLE_NETWORK_MODE *Mode;\r
- UINT32 MultHashTableHigh;\r
- UINT32 MultHashTableLow;\r
- UINT32 Count;\r
- UINT32 Crc;\r
- UINT8 HashValue;\r
- UINT32 MacCSRValue;\r
- UINT32 ReceiveFilterSetting;\r
- EFI_MAC_ADDRESS *Mac;\r
- EFI_MAC_ADDRESS ZeroMac;\r
-\r
- // Check Snp Instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- Mode = Snp->Mode;\r
-\r
- // Check that driver was started and initialised\r
- if (Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- if ((Enable & (~Mode->ReceiveFilterMask)) ||\r
- (Disable & (~Mode->ReceiveFilterMask)) ) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check the validity of the multicast setting and compute the\r
- // hash values of the multicast mac addresses to listen to.\r
- //\r
-\r
- MultHashTableHigh = 0;\r
- MultHashTableLow = 0;\r
- if ((!ResetMCastFilter) &&\r
- ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) == 0) &&\r
- ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) != 0) ) {\r
- if ((MCastFilterCnt == 0) ||\r
- (MCastFilterCnt > Mode->MaxMCastFilterCount) ||\r
- (MCastFilter == NULL) ) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- //\r
- // Check the validity of all multicast addresses before to change\r
- // anything.\r
- //\r
- for (Count = 0; Count < MCastFilterCnt; Count++) {\r
- if ((MCastFilter[Count].Addr[0] & 1) == 0) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- }\r
-\r
- //\r
- // Go through each filter address and set appropriate bits on hash table\r
- //\r
- for (Count = 0; Count < MCastFilterCnt; Count++) {\r
- Mac = &(MCastFilter[Count]);\r
- CopyMem (&Mode->MCastFilter[Count], Mac, sizeof(EFI_MAC_ADDRESS));\r
-\r
- Crc = GenEtherCrc32 (Mac, NET_ETHER_ADDR_LEN);\r
- //gBS->CalculateCrc32 ((VOID*)&Mfilter[Count],6,&Crc); <-- doesn't work as desired\r
-\r
- //\r
- // The most significant 6 bits of the MAC address CRC constitute the hash\r
- // value of the MAC address.\r
- //\r
- HashValue = (Crc >> 26) & 0x3F;\r
-\r
- // Select hashlow register if MSB is not set\r
- if ((HashValue & 0x20) == 0) {\r
- MultHashTableLow |= (1 << HashValue);\r
- } else {\r
- MultHashTableHigh |= (1 << (HashValue & 0x1F));\r
- }\r
- }\r
- Mode->MCastFilterCount = MCastFilterCnt;\r
- } else if (ResetMCastFilter) {\r
- Mode->MCastFilterCount = 0;\r
- } else {\r
- MultHashTableLow = IndirectMACRead32 (INDIRECT_MAC_INDEX_HASHL);\r
- MultHashTableHigh = IndirectMACRead32 (INDIRECT_MAC_INDEX_HASHH);\r
- }\r
-\r
- //\r
- // Before to change anything, stop and reset the reception of\r
- // packets.\r
- //\r
- StopRx (STOP_RX_CLEAR, Snp);\r
-\r
- //\r
- // Write the mask of the selected hash values for the multicast filtering.\r
- // The two masks are set to zero if the multicast filtering is not enabled.\r
- //\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_HASHL, MultHashTableLow);\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_HASHH, MultHashTableHigh);\r
-\r
- ReceiveFilterSetting = (Mode->ReceiveFilterSetting | Enable) & (~Disable);\r
-\r
- //\r
- // Read MAC controller\r
- //\r
- MacCSRValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- MacCSRValue &= ~(MACCR_HPFILT | MACCR_BCAST | MACCR_PRMS | MACCR_MCPAS);\r
-\r
- if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_UNICAST) {\r
- Lan9118SetMacAddress (&Mode->CurrentAddress, Snp);\r
- DEBUG ((DEBUG_NET, "Allowing Unicast Frame Reception\n"));\r
- } else {\r
- //\r
- // The Unicast packets do not have to be listen to, set the MAC\r
- // address of the LAN9118 to be the "not configured" all zeroes\r
- // ethernet MAC address.\r
- //\r
- ZeroMem (&ZeroMac, NET_ETHER_ADDR_LEN);\r
- Lan9118SetMacAddress (&ZeroMac, Snp);\r
- }\r
-\r
- if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) {\r
- MacCSRValue |= MACCR_HPFILT;\r
- DEBUG ((DEBUG_NET, "Allowing Multicast Frame Reception\n"));\r
- }\r
-\r
- if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) {\r
- MacCSRValue |= MACCR_MCPAS;\r
- DEBUG ((DEBUG_NET, "Enabling Promiscuous Multicast Mode\n"));\r
- }\r
-\r
- if ((ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST) == 0) {\r
- MacCSRValue |= MACCR_BCAST;\r
- } else {\r
- DEBUG ((DEBUG_NET, "Allowing Broadcast Frame Reception\n"));\r
- }\r
-\r
- if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) {\r
- MacCSRValue |= MACCR_PRMS;\r
- DEBUG ((DEBUG_NET, "Enabling Promiscuous Mode\n"));\r
- }\r
-\r
- //\r
- // Write the options to the MAC_CSR\r
- //\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCSRValue);\r
-\r
- //\r
- // If we have to retrieve something, start packet reception.\r
- //\r
- Mode->ReceiveFilterSetting = ReceiveFilterSetting;\r
- if (ReceiveFilterSetting != 0) {\r
- StartRx (0, Snp);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Modify of reset the current station address\r
-\r
- @param[in] Snp A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL\r
- instance.\r
- @param[in] Reset Flag used to reset the station address to the\r
- LAN9118's permanent address.\r
- @param[in] New New station address to be used for the network interface.\r
-\r
- @retval EFI_SUCCESS The LAN9118's station address was updated.\r
- @retval EFI_NOT_STARTED The LAN9118 has not been started.\r
- @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE :\r
- . The "New" station address is invalid.\r
- . "Reset" is FALSE and "New" is NULL.\r
- @retval EFI_DEVICE_ERROR The LAN9118 has been started but not initialized.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStationAddress (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,\r
- IN BOOLEAN Reset,\r
- IN EFI_MAC_ADDRESS *New\r
-)\r
-{\r
- UINT32 Count;\r
- UINT8 PermAddr[NET_ETHER_ADDR_LEN];\r
-\r
- DEBUG ((DEBUG_NET, "SnpStationAddress()\n"));\r
-\r
- // Check Snp instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Get the Permanent MAC address if need reset\r
- if (Reset) {\r
- // Try using EEPROM first. Read the first byte of data from EEPROM at the address 0x0\r
- if ((IndirectEEPROMRead32 (0) & 0xFF) == EEPROM_EXTERNAL_SERIAL_EEPROM) {\r
- for (Count = 0; Count < NET_ETHER_ADDR_LEN; Count++) {\r
- PermAddr[Count] = IndirectEEPROMRead32 (Count + 1);\r
- }\r
- New = (EFI_MAC_ADDRESS *) PermAddr;\r
- Lan9118SetMacAddress ((EFI_MAC_ADDRESS *) PermAddr, Snp);\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "LAN9118: Warning: No valid MAC address in EEPROM, using fallback\n"));\r
- New = (EFI_MAC_ADDRESS*) (FixedPcdGet64 (PcdLan9118DefaultMacAddress));\r
- }\r
- } else {\r
- // Otherwise use the specified new MAC address\r
- if (New == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- //\r
- // If it is a multicast address, it is not valid.\r
- //\r
- if (New->Addr[0] & 0x01) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- }\r
-\r
- CopyMem (&Snp->Mode->CurrentAddress, New, NET_ETHER_ADDR_LEN);\r
-\r
- //\r
- // If packet reception is currently activated, stop and reset it,\r
- // set the new ethernet address and restart the packet reception.\r
- // Otherwise, nothing to do, the MAC address will be updated in\r
- // SnpReceiveFilters() when the UNICAST packet reception will be\r
- // activated.\r
- //\r
- if (Snp->Mode->ReceiveFilterSetting != 0) {\r
- StopRx (STOP_RX_CLEAR, Snp);\r
- Lan9118SetMacAddress (New, Snp);\r
- StartRx (0, Snp);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- * UEFI Statistics() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStatistics (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN Reset,\r
- IN OUT UINTN *StatSize,\r
- OUT EFI_NETWORK_STATISTICS *Statistics\r
- )\r
-{\r
- LAN9118_DRIVER *LanDriver;\r
- EFI_STATUS Status;\r
-\r
- LanDriver = INSTANCE_FROM_SNP_THIS (Snp);\r
-\r
- DEBUG ((DEBUG_NET, "SnpStatistics()\n"));\r
-\r
- // Check Snp instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- //\r
- // Do a reset if required. It is not clearly stated in the UEFI specification\r
- // whether the reset has to be done before to copy the statistics in "Statictics"\r
- // or after. It is a bit strange to do it before but that is what is expected by\r
- // the SCT test on Statistics() with reset : "0x3de76704,0x4bf5,0x42cd,0x8c,0x89,\r
- // 0x54,0x7e,0x4f,0xad,0x4f,0x24".\r
- //\r
- if (Reset) {\r
- ZeroMem (&LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS));\r
- }\r
-\r
- Status = EFI_SUCCESS;\r
- if (StatSize == NULL) {\r
- if (Statistics != NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- } else {\r
- if (Statistics == NULL) {\r
- Status = EFI_BUFFER_TOO_SMALL;\r
- } else {\r
- // Fill in the statistics\r
- CopyMem (\r
- Statistics, &LanDriver->Stats,\r
- MIN (*StatSize, sizeof (EFI_NETWORK_STATISTICS))\r
- );\r
- if (*StatSize < sizeof (EFI_NETWORK_STATISTICS)) {\r
- Status = EFI_BUFFER_TOO_SMALL;\r
- }\r
- }\r
- *StatSize = sizeof (EFI_NETWORK_STATISTICS);\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/*\r
- * UEFI MCastIPtoMAC() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpMcastIptoMac (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN IsIpv6,\r
- IN EFI_IP_ADDRESS *Ip,\r
- OUT EFI_MAC_ADDRESS *McastMac\r
- )\r
-{\r
- DEBUG ((DEBUG_NET, "SnpMcastIptoMac()\n"));\r
-\r
- // Check Snp instance\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Check parameters\r
- if ((McastMac == NULL) || (Ip == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Make sure MAC address is empty\r
- ZeroMem (McastMac, sizeof(EFI_MAC_ADDRESS));\r
-\r
- // If we need ipv4 address\r
- if (!IsIpv6) {\r
- // Most significant 25 bits of a multicast HW address are set.\r
- // 01-00-5E is the IPv4 Ethernet Multicast Address (see RFC 1112)\r
- McastMac->Addr[0] = 0x01;\r
- McastMac->Addr[1] = 0x00;\r
- McastMac->Addr[2] = 0x5E;\r
-\r
- // Lower 23 bits from ipv4 address\r
- McastMac->Addr[3] = (Ip->v4.Addr[1] & 0x7F); // Clear the most significant bit (25th bit of MAC must be 0)\r
- McastMac->Addr[4] = Ip->v4.Addr[2];\r
- McastMac->Addr[5] = Ip->v4.Addr[3];\r
- } else {\r
- // Most significant 16 bits of multicast v6 HW address are set\r
- // 33-33 is the IPv6 Ethernet Multicast Address (see RFC 2464)\r
- McastMac->Addr[0] = 0x33;\r
- McastMac->Addr[1] = 0x33;\r
-\r
- // lower four octets are taken from ipv6 address\r
- McastMac->Addr[2] = Ip->v6.Addr[8];\r
- McastMac->Addr[3] = Ip->v6.Addr[9];\r
- McastMac->Addr[4] = Ip->v6.Addr[10];\r
- McastMac->Addr[5] = Ip->v6.Addr[11];\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- * UEFI NvData() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpNvData (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* pobj,\r
- IN BOOLEAN read_write,\r
- IN UINTN offset,\r
- IN UINTN buff_size,\r
- IN OUT VOID *data\r
- )\r
-{\r
- DEBUG ((DEBUG_NET, "SnpNvData()\n"));\r
-\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-\r
-/*\r
- * UEFI GetStatus () function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpGetStatus (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,\r
- OUT UINT32 *IrqStat OPTIONAL,\r
- OUT VOID **TxBuff OPTIONAL\r
- )\r
-{\r
- UINT32 FifoInt;\r
- EFI_STATUS Status;\r
- UINTN NumTxStatusEntries;\r
- UINT32 TxStatus;\r
- UINT16 PacketTag;\r
- UINT32 Interrupts;\r
- LAN9118_DRIVER *LanDriver;\r
-\r
- LanDriver = INSTANCE_FROM_SNP_THIS (Snp);\r
-\r
- // Check preliminaries\r
- if (Snp == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Check and acknowledge TX Status interrupt (this will happen if the\r
- // consumer of SNP does not call GetStatus.)\r
- // TODO will we lose TxStatuses if this happens? Maybe in SnpTransmit we\r
- // should check for it and dump the TX Status FIFO.\r
- FifoInt = Lan9118MmioRead32 (LAN9118_FIFO_INT);\r
-\r
- // Clear the TX Status FIFO Overflow\r
- if ((FifoInt & INSTS_TXSO) == 0) {\r
- FifoInt |= INSTS_TXSO;\r
- Lan9118MmioWrite32 (LAN9118_FIFO_INT, FifoInt);\r
- }\r
-\r
- // Read interrupt status if IrqStat is not NULL\r
- if (IrqStat != NULL) {\r
- *IrqStat = 0;\r
-\r
- // Check for receive interrupt\r
- if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RSFL) { // Data moved from rx FIFO\r
- *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;\r
- Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_RSFL);\r
- }\r
-\r
- // Check for transmit interrupt\r
- if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_TSFL) {\r
- *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;\r
- Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_TSFL);\r
- }\r
-\r
- // Check for software interrupt\r
- if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_SW_INT) {\r
- *IrqStat |= EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT;\r
- Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_SW_INT);\r
- }\r
- }\r
-\r
- // Check Status of transmitted packets\r
- // (We ignore TXSTATUS_NO_CA has it might happen in Full Duplex)\r
-\r
- NumTxStatusEntries = Lan9118MmioRead32(LAN9118_TX_FIFO_INF) & TXFIFOINF_TXSUSED_MASK;\r
- if (NumTxStatusEntries > 0) {\r
- TxStatus = Lan9118MmioRead32 (LAN9118_TX_STATUS);\r
- PacketTag = TxStatus >> 16;\r
- TxStatus = TxStatus & 0xFFFF;\r
- if ((TxStatus & TXSTATUS_ES) && (TxStatus != (TXSTATUS_ES | TXSTATUS_NO_CA))) {\r
- DEBUG ((EFI_D_ERROR, "LAN9118: There was an error transmitting. TxStatus=0x%08x:", TxStatus));\r
- if (TxStatus & TXSTATUS_NO_CA) {\r
- DEBUG ((EFI_D_ERROR, "- No carrier\n"));\r
- }\r
- if (TxStatus & TXSTATUS_DEF) {\r
- DEBUG ((EFI_D_ERROR, "- Packet tx was deferred\n"));\r
- }\r
- if (TxStatus & TXSTATUS_EDEF) {\r
- DEBUG ((EFI_D_ERROR, "- Tx ended because of excessive deferral\n"));\r
- }\r
- if (TxStatus & TXSTATUS_ECOLL) {\r
- DEBUG ((EFI_D_ERROR, "- Tx ended because of Excessive Collisions\n"));\r
- }\r
- if (TxStatus & TXSTATUS_LCOLL) {\r
- DEBUG ((EFI_D_ERROR, "- Packet Tx aborted after coll window of 64 bytes\n"));\r
- }\r
- if (TxStatus & TXSTATUS_LOST_CA) {\r
- DEBUG ((EFI_D_ERROR, "- Lost carrier during Tx\n"));\r
- }\r
- return EFI_DEVICE_ERROR;\r
- } else if (TxBuff != NULL) {\r
- LanDriver->Stats.TxTotalFrames += 1;\r
- *TxBuff = LanDriver->TxRing[PacketTag % LAN9118_TX_RING_NUM_ENTRIES];\r
- }\r
- } else if (TxBuff != NULL) {\r
- *TxBuff = NULL;\r
- }\r
-\r
- // Check for a TX Error interrupt\r
- Interrupts = Lan9118MmioRead32 (LAN9118_INT_STS);\r
- if (Interrupts & INSTS_TXE) {\r
- DEBUG ((EFI_D_ERROR, "LAN9118: Transmitter error. Restarting..."));\r
-\r
- // Software reset, the TXE interrupt is cleared by the reset.\r
- Status = SoftReset (0, Snp);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "\n\tSoft Reset Failed: Hardware Error\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Reactivate the LEDs\r
- Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Restart the transmitter and if necessary the receiver.\r
- // Do not ask for FIFO reset as it has already been done\r
- // by SoftReset().\r
- //\r
- StartTx (START_TX_MAC | START_TX_CFG, Snp);\r
- if (Snp->Mode->ReceiveFilterSetting != 0) {\r
- StartRx (0, Snp);\r
- }\r
- }\r
-\r
- // Update the media status\r
- Status = CheckLinkStatus (0, Snp);\r
- if (EFI_ERROR(Status)) {\r
- Snp->Mode->MediaPresent = FALSE;\r
- } else {\r
- Snp->Mode->MediaPresent = TRUE;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/*\r
- * UEFI Transmit() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpTransmit (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,\r
- IN UINTN HdrSize,\r
- IN UINTN BuffSize,\r
- IN VOID* Data,\r
- IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,\r
- IN EFI_MAC_ADDRESS *DstAddr OPTIONAL,\r
- IN UINT16 *Protocol OPTIONAL\r
- )\r
-{\r
- LAN9118_DRIVER *LanDriver;\r
- UINT32 TxFreeSpace;\r
- UINT32 TxStatusSpace;\r
- INT32 Count;\r
- UINT32 CommandA;\r
- UINT32 CommandB;\r
- UINT16 LocalProtocol;\r
- UINT32 *LocalData;\r
- UINT16 PacketTag;\r
-\r
-#if defined(EVAL_PERFORMANCE)\r
- UINT64 Perf;\r
- UINT64 StartClock;\r
- UINT64 EndClock;\r
-\r
- Perf = GetPerformanceCounterProperties (NULL, NULL);\r
- StartClock = GetPerformanceCounter ();\r
-#endif\r
-\r
- LanDriver = INSTANCE_FROM_SNP_THIS (Snp);\r
-\r
- // Check preliminaries\r
- if ((Snp == NULL) || (Data == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- // Ensure header is correct size if non-zero\r
- if (HdrSize) {\r
- if (HdrSize != Snp->Mode->MediaHeaderSize) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((DstAddr == NULL) || (Protocol == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- }\r
-\r
- //\r
- // Check validity of BufferSize\r
- //\r
- if (BuffSize < Snp->Mode->MediaHeaderSize) {\r
- return EFI_BUFFER_TOO_SMALL;\r
- }\r
-\r
- // Before transmitting check the link status\r
- /*if (CheckLinkStatus (0, Snp) < 0) {\r
- return EFI_NOT_READY;\r
- }*/\r
-\r
- // Get DATA FIFO free space in bytes\r
- TxFreeSpace = TxDataFreeSpace (0, Snp);\r
- if (TxFreeSpace < BuffSize) {\r
- return EFI_NOT_READY;\r
- }\r
-\r
- // Get STATUS FIFO used space in bytes\r
- TxStatusSpace = TxStatusUsedSpace (0, Snp);\r
- if (TxStatusSpace > 500) {\r
- return EFI_NOT_READY;\r
- }\r
-\r
- // If DstAddr is not provided, get it from Buffer (we trust that the caller\r
- // has provided a well-formed frame).\r
- if (DstAddr == NULL) {\r
- DstAddr = (EFI_MAC_ADDRESS *) Data;\r
- }\r
-\r
- // Check for the nature of the frame\r
- if ((DstAddr->Addr[0] & 0x1) == 1) {\r
- LanDriver->Stats.TxMulticastFrames += 1;\r
- } else {\r
- LanDriver->Stats.TxUnicastFrames += 1;\r
- }\r
-\r
- // Check if broadcast\r
- if (DstAddr->Addr[0] == 0xFF) {\r
- LanDriver->Stats.TxBroadcastFrames += 1;\r
- }\r
-\r
- PacketTag = LanDriver->NextPacketTag;\r
- LanDriver->NextPacketTag++;\r
-\r
- if (HdrSize) {\r
-\r
- // Format pointer\r
- LocalData = (UINT32*) Data;\r
- LocalProtocol = *Protocol;\r
-\r
- // Create first buffer to pass to controller (for the header)\r
- CommandA = TX_CMD_A_FIRST_SEGMENT | TX_CMD_A_BUFF_SIZE (HdrSize);\r
- CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize);\r
-\r
- // Write the commands first\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
-\r
- // Write the destination address\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
- (DstAddr->Addr[0]) |\r
- (DstAddr->Addr[1] << 8) |\r
- (DstAddr->Addr[2] << 16) |\r
- (DstAddr->Addr[3] << 24)\r
- );\r
-\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
- (DstAddr->Addr[4]) |\r
- (DstAddr->Addr[5] << 8) |\r
- (SrcAddr->Addr[0] << 16) | // Write the Source Address\r
- (SrcAddr->Addr[1] << 24)\r
- );\r
-\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
- (SrcAddr->Addr[2]) |\r
- (SrcAddr->Addr[3] << 8) |\r
- (SrcAddr->Addr[4] << 16) |\r
- (SrcAddr->Addr[5] << 24)\r
- );\r
-\r
- // Write the Protocol\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, (UINT32)(HTONS (LocalProtocol)));\r
-\r
- // Next buffer is the payload\r
- CommandA = TX_CMD_A_LAST_SEGMENT | TX_CMD_A_BUFF_SIZE (BuffSize - HdrSize) | TX_CMD_A_COMPLETION_INT | TX_CMD_A_DATA_START_OFFSET (2); // 2 bytes beginning offset\r
-\r
- // Write the commands\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
-\r
- // Write the payload\r
- for (Count = 0; Count < ((BuffSize + 3) >> 2) - 3; Count++) {\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count + 3]);\r
- }\r
- } else {\r
- // Format pointer\r
- LocalData = (UINT32*) Data;\r
-\r
- // Create a buffer to pass to controller\r
- CommandA = TX_CMD_A_FIRST_SEGMENT | TX_CMD_A_LAST_SEGMENT | TX_CMD_A_BUFF_SIZE (BuffSize) | TX_CMD_A_COMPLETION_INT;\r
- CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize);\r
-\r
- // Write the commands first\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
-\r
- // Write all the data\r
- for (Count = 0; Count < ((BuffSize + 3) >> 2); Count++) {\r
- Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count]);\r
- }\r
- }\r
-\r
- // Save the address of the submitted packet so we can notify the consumer that\r
- // it has been sent in GetStatus. When the packet tag appears in the Tx Status\r
- // Fifo, we will return Buffer in the TxBuff parameter of GetStatus.\r
- LanDriver->TxRing[PacketTag % LAN9118_TX_RING_NUM_ENTRIES] = Data;\r
-\r
-#if defined(EVAL_PERFORMANCE)\r
- EndClock = GetPerformanceCounter ();\r
- DEBUG ((EFI_D_ERROR, "Time processing: %d counts @ %d Hz\n", StartClock - EndClock,Perf));\r
-#endif\r
-\r
- LanDriver->Stats.TxGoodFrames += 1;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/*\r
- * UEFI Receive() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReceive (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- OUT UINTN *HdrSize OPTIONAL,\r
- IN OUT UINTN *BuffSize,\r
- OUT VOID *Data,\r
- OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,\r
- OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,\r
- OUT UINT16 *Protocol OPTIONAL\r
- )\r
-{\r
- LAN9118_DRIVER *LanDriver;\r
- UINT32 IntSts;\r
- UINT32 RxFifoStatus;\r
- UINT32 NumPackets;\r
- UINT32 RxCfgValue;\r
- UINT32 PLength; // Packet length\r
- UINT32 ReadLimit;\r
- UINT32 Count;\r
- UINT32 Padding;\r
- UINT32 *RawData;\r
- EFI_MAC_ADDRESS Dst;\r
- EFI_MAC_ADDRESS Src;\r
- UINTN DroppedFrames;\r
- EFI_STATUS Status;\r
-\r
- LanDriver = INSTANCE_FROM_SNP_THIS (Snp);\r
-\r
-#if defined(EVAL_PERFORMANCE)\r
- UINT64 Perf = GetPerformanceCounterProperties (NULL, NULL);\r
- UINT64 StartClock = GetPerformanceCounter ();\r
-#endif\r
-\r
- // Check preliminaries\r
- if ((Snp == NULL) || (Data == NULL) || (BuffSize == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Check that driver was started and initialised\r
- if (Snp->Mode->State == EfiSimpleNetworkStarted) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver not initialized\n"));\r
- return EFI_DEVICE_ERROR;\r
- } else if (Snp->Mode->State == EfiSimpleNetworkStopped) {\r
- DEBUG ((EFI_D_WARN, "Warning: LAN9118 Driver in stopped state\n"));\r
- return EFI_NOT_STARTED;\r
- }\r
-\r
- //\r
- // If the receiver raised the RXE error bit, check if the receiver status\r
- // FIFO is full and if not just acknowledge the error. The two other\r
- // conditions to get a RXE error are :\r
- // . the RX data FIFO is read whereas being empty.\r
- // . the RX status FIFO is read whereas being empty.\r
- // The RX data and status FIFO are read by this driver only in the following\r
- // code of this function. After the readings, the RXE error bit is checked\r
- // and if raised, the controller is reset. Thus, at this point, we consider\r
- // that the only valid reason to get an RXE error is the receiver status\r
- // FIFO being full. And if this is not the case, we consider that this is\r
- // a spurious error and we just get rid of it. We experienced such 'spurious'\r
- // errors when running the driver on an A57 on Juno. No valid reason to\r
- // explain those errors has been found so far and everything seems to\r
- // work perfectly when they are just ignored.\r
- //\r
- IntSts = Lan9118MmioRead32 (LAN9118_INT_STS);\r
- if ((IntSts & INSTS_RXE) && (!(IntSts & INSTS_RSFF))) {\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, INSTS_RXE);\r
- }\r
-\r
- // Count dropped frames\r
- DroppedFrames = Lan9118MmioRead32 (LAN9118_RX_DROP);\r
- LanDriver->Stats.RxDroppedFrames += DroppedFrames;\r
-\r
- NumPackets = RxStatusUsedSpace (0, Snp) / 4;\r
- if (!NumPackets) {\r
- return EFI_NOT_READY;\r
- }\r
-\r
- // Read Rx Status (only if not empty)\r
- RxFifoStatus = Lan9118MmioRead32 (LAN9118_RX_STATUS);\r
- LanDriver->Stats.RxTotalFrames += 1;\r
-\r
- // First check for errors\r
- if ((RxFifoStatus & RXSTATUS_MII_ERROR) ||\r
- (RxFifoStatus & RXSTATUS_RXW_TO) ||\r
- (RxFifoStatus & RXSTATUS_FTL) ||\r
- (RxFifoStatus & RXSTATUS_LCOLL) ||\r
- (RxFifoStatus & RXSTATUS_LE) ||\r
- (RxFifoStatus & RXSTATUS_DB))\r
- {\r
- DEBUG ((EFI_D_WARN, "Warning: There was an error on frame reception.\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Check if we got a CRC error\r
- if (RxFifoStatus & RXSTATUS_CRC_ERROR) {\r
- DEBUG ((EFI_D_WARN, "Warning: Crc Error\n"));\r
- LanDriver->Stats.RxCrcErrorFrames += 1;\r
- LanDriver->Stats.RxDroppedFrames += 1;\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Check if we got a runt frame\r
- if (RxFifoStatus & RXSTATUS_RUNT) {\r
- DEBUG ((EFI_D_WARN, "Warning: Runt Frame\n"));\r
- LanDriver->Stats.RxUndersizeFrames += 1;\r
- LanDriver->Stats.RxDroppedFrames += 1;\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Check filtering status for this packet\r
- if (RxFifoStatus & RXSTATUS_FILT_FAIL) {\r
- DEBUG ((EFI_D_WARN, "Warning: Frame Failed Filtering\n"));\r
- // fast forward?\r
- }\r
-\r
- // Check if we got a broadcast frame\r
- if (RxFifoStatus & RXSTATUS_BCF) {\r
- LanDriver->Stats.RxBroadcastFrames += 1;\r
- }\r
-\r
- // Check if we got a multicast frame\r
- if (RxFifoStatus & RXSTATUS_MCF) {\r
- LanDriver->Stats.RxMulticastFrames += 1;\r
- }\r
-\r
- // Check if we got a unicast frame\r
- if ((RxFifoStatus & RXSTATUS_BCF) && ((RxFifoStatus & RXSTATUS_MCF) == 0)) {\r
- LanDriver->Stats.RxUnicastFrames += 1;\r
- }\r
-\r
- // Get the received packet length\r
- PLength = GET_RXSTATUS_PACKET_LENGTH(RxFifoStatus);\r
- LanDriver->Stats.RxTotalBytes += (PLength - 4);\r
-\r
- // If padding is applied, read more DWORDs\r
- if (PLength % 4) {\r
- Padding = 4 - (PLength % 4);\r
- ReadLimit = (PLength + Padding)/4;\r
- } else {\r
- ReadLimit = PLength/4;\r
- Padding = 0;\r
- }\r
-\r
- // Check buffer size\r
- if (*BuffSize < (PLength + Padding)) {\r
- *BuffSize = PLength + Padding;\r
- return EFI_BUFFER_TOO_SMALL;\r
- }\r
-\r
- // Set the amount of data to be transferred out of FIFO for THIS packet\r
- // This can be used to trigger an interrupt, and status can be checked\r
- RxCfgValue = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
- RxCfgValue &= ~(RXCFG_RX_DMA_CNT_MASK);\r
- RxCfgValue |= RXCFG_RX_DMA_CNT (ReadLimit);\r
-\r
- // Set end alignment to 4-bytes\r
- RxCfgValue &= ~(RXCFG_RX_END_ALIGN_MASK);\r
- Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfgValue);\r
-\r
- // Update buffer size\r
- *BuffSize = PLength; // -4 bytes may be needed: Received in buffer as\r
- // 4 bytes longer than packet actually is, unless\r
- // packet is < 64 bytes\r
-\r
- if (HdrSize != NULL)\r
- *HdrSize = Snp->Mode->MediaHeaderSize;\r
-\r
- // Format the pointer\r
- RawData = (UINT32*)Data;\r
-\r
- // Read Rx Packet\r
- for (Count = 0; Count < ReadLimit; Count++) {\r
- RawData[Count] = Lan9118MmioRead32 (LAN9118_RX_DATA);\r
- }\r
-\r
- // Get the destination address\r
- if (DstAddr != NULL) {\r
- Dst.Addr[0] = (RawData[0] & 0xFF);\r
- Dst.Addr[1] = (RawData[0] & 0xFF00) >> 8;\r
- Dst.Addr[2] = (RawData[0] & 0xFF0000) >> 16;\r
- Dst.Addr[3] = (RawData[0] & 0xFF000000) >> 24;\r
- Dst.Addr[4] = (RawData[1] & 0xFF);\r
- Dst.Addr[5] = (RawData[1] & 0xFF00) >> 8;\r
- CopyMem (DstAddr, &Dst, NET_ETHER_ADDR_LEN);\r
- }\r
-\r
- // Get the source address\r
- if (SrcAddr != NULL) {\r
- Src.Addr[0] = (RawData[1] & 0xFF0000) >> 16;\r
- Src.Addr[1] = (RawData[1] & 0xFF000000) >> 24;\r
- Src.Addr[2] = (RawData[2] & 0xFF);\r
- Src.Addr[3] = (RawData[2] & 0xFF00) >> 8;\r
- Src.Addr[4] = (RawData[2] & 0xFF0000) >> 16;\r
- Src.Addr[5] = (RawData[2] & 0xFF000000) >> 24;\r
- CopyMem (SrcAddr, &Src, NET_ETHER_ADDR_LEN);\r
- }\r
-\r
- // Get the protocol\r
- if (Protocol != NULL) {\r
- *Protocol = NTOHS (RawData[3] & 0xFFFF);\r
- }\r
-\r
- // Check for Rx errors (worst possible error)\r
- if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RXE) {\r
- DEBUG ((EFI_D_WARN, "Warning: Receiver Error. Restarting...\n"));\r
-\r
- // Software reset, the RXE interrupt is cleared by the reset.\r
- Status = SoftReset (0, Snp);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Error: Soft Reset Failed: Hardware Error.\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Reactivate the LEDs\r
- Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Restart the receiver and the transmitter without resetting the FIFOs\r
- // as it has been done by SoftReset().\r
- //\r
- StartRx (0, Snp);\r
- StartTx (START_TX_MAC | START_TX_CFG, Snp);\r
-\r
- // Say that command could not be sent\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
-#if defined(EVAL_PERFORMANCE)\r
- UINT64 EndClock = GetPerformanceCounter ();\r
- DEBUG ((EFI_D_ERROR, "Receive Time processing: %d counts @ %d Hz\n", StartClock - EndClock,Perf));\r
-#endif\r
-\r
- LanDriver->Stats.RxGoodFrames += 1;\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#ifndef __LAN9118_DXE_H__\r
-#define __LAN9118_DXE_H__\r
-\r
-#include <Uefi.h>\r
-#include <Uefi/UefiSpec.h>\r
-#include <Base.h>\r
-\r
-// Protocols used by this driver\r
-#include <Protocol/SimpleNetwork.h>\r
-#include <Protocol/ComponentName2.h>\r
-#include <Protocol/PxeBaseCode.h>\r
-#include <Protocol/DevicePath.h>\r
-\r
-// Libraries used by this driver\r
-#include <Library/UefiLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/NetLib.h>\r
-#include <Library/DevicePathLib.h>\r
-\r
-#include "Lan9118DxeUtil.h"\r
-#include "Lan9118DxeHw.h"\r
-\r
-#define LAN9118_STALL 2\r
-\r
-#define LAN9118_DEFAULT_MAC_ADDRL 0x00F70200\r
-#define LAN9118_DEFAULT_MAC_ADDRH 0x00009040\r
-\r
-#define LAN9118_TX_DATA_SIZE 4608\r
-#define LAN9118_TX_STATUS_SIZE 512\r
-#define LAN9118_RX_DATA_SIZE 10560\r
-#define LAN9118_RX_STATUS_SIZE 704\r
-\r
-#define LAN9118_TX_RING_NUM_ENTRIES 32\r
-\r
-/*------------------------------------------------------------------------------\r
- LAN9118 Information Structure\r
-------------------------------------------------------------------------------*/\r
-\r
-typedef struct {\r
- // Driver signature\r
- UINT32 Signature;\r
- EFI_HANDLE ControllerHandle;\r
-\r
- // EFI SNP protocol instances\r
- EFI_SIMPLE_NETWORK_PROTOCOL Snp;\r
- EFI_SIMPLE_NETWORK_MODE SnpMode;\r
-\r
- // EFI Snp statistics instance\r
- EFI_NETWORK_STATISTICS Stats;\r
-\r
- // Saved transmitted buffers so we can notify consumers when packets have been sent.\r
- UINT16 NextPacketTag;\r
- VOID *TxRing[LAN9118_TX_RING_NUM_ENTRIES];\r
-} LAN9118_DRIVER;\r
-\r
-#define LAN9118_SIGNATURE SIGNATURE_32('l', 'a', 'n', '9')\r
-#define INSTANCE_FROM_SNP_THIS(a) CR(a, LAN9118_DRIVER, Snp, LAN9118_SIGNATURE)\r
-\r
-\r
-/*---------------------------------------------------------------------------------------------------------------------\r
-\r
- UEFI-Compliant functions for EFI_SIMPLE_NETWORK_PROTOCOL\r
-\r
- Refer to the Simple Network Protocol section (21.1) in the UEFI 2.3.1 Specification for related definitions\r
-\r
----------------------------------------------------------------------------------------------------------------------*/\r
-\r
-\r
-/*\r
- * UEFI Start() function\r
- *\r
- * Parameters:\r
- *\r
- * @param pobj: A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.\r
- *\r
- * Description:\r
- *\r
- * This function starts a network interface. If the network interface successfully starts, then\r
- * EFI_SUCCESS will be returned.\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStart (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp\r
- );\r
-\r
-/*\r
- * UEFI Stop() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStop (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp\r
- );\r
-\r
-/*\r
- * UEFI Initialize() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpInitialize (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN UINTN rx_buff_size,\r
- IN UINTN tx_buff_size\r
- );\r
-\r
-/*\r
- * UEFI Reset() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReset (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN ext_ver\r
- );\r
-\r
-/*\r
- * UEFI Shutdown() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpShutdown (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp\r
- );\r
-\r
-/*\r
- * UEFI ReceiveFilters() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReceiveFilters (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN UINT32 enable,\r
- IN UINT32 disable,\r
- IN BOOLEAN reset_mfilter,\r
- IN UINTN num_mfilter,\r
- IN EFI_MAC_ADDRESS *mfilter\r
- );\r
-\r
-/*\r
- * UEFI StationAddress() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStationAddress (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN reset,\r
- IN EFI_MAC_ADDRESS *new_maddr\r
- );\r
-\r
-/*\r
- * UEFI Statistics() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpStatistics (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN reset,\r
- IN OUT UINTN *stat_size,\r
- OUT EFI_NETWORK_STATISTICS *stat_table\r
- );\r
-\r
-/*\r
- * UEFI MCastIPtoMAC() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpMcastIptoMac (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN use_ipv6,\r
- IN EFI_IP_ADDRESS *ip_addr,\r
- OUT EFI_MAC_ADDRESS *mac_addr\r
- );\r
-\r
-/*\r
- * UEFI NvData() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpNvData (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN BOOLEAN read_write,\r
- IN UINTN offset,\r
- IN UINTN buff_size,\r
- IN OUT VOID *data\r
- );\r
-\r
-/*\r
- * UEFI GetStatus() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpGetStatus (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- OUT UINT32 *irq_stat OPTIONAL,\r
- OUT VOID **tx_buff OPTIONAL\r
- );\r
-\r
-/*\r
- * UEFI Transmit() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpTransmit (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- IN UINTN hdr_size,\r
- IN UINTN buff_size,\r
- IN VOID *data,\r
- IN EFI_MAC_ADDRESS *src_addr OPTIONAL,\r
- IN EFI_MAC_ADDRESS *dest_addr OPTIONAL,\r
- IN UINT16 *protocol OPTIONAL\r
- );\r
-\r
-/*\r
- * UEFI Receive() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpReceive (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp,\r
- OUT UINTN *hdr_size OPTIONAL,\r
- IN OUT UINTN *buff_size,\r
- OUT VOID *data,\r
- OUT EFI_MAC_ADDRESS *src_addr OPTIONAL,\r
- OUT EFI_MAC_ADDRESS *dest_addr OPTIONAL,\r
- OUT UINT16 *protocol OPTIONAL\r
- );\r
-\r
-\r
-/*---------------------------------------------------------------------------------------------------------------------\r
-\r
- UEFI-Compliant functions for EFI_COMPONENT_NAME2_PROTOCOL\r
-\r
- Refer to the Component Name Protocol section (10.5) in the UEFI 2.3.1 Specification for related definitions\r
-\r
----------------------------------------------------------------------------------------------------------------------*/\r
-\r
-/*\r
- * UEFI GetDriverName() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpGetDriverName (\r
- IN EFI_COMPONENT_NAME2_PROTOCOL *Snp,\r
- IN CHAR8 *Lang,\r
- OUT CHAR16 **DriverName\r
- );\r
-\r
-/*\r
- * UEFI GetControllerName() function\r
- *\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-SnpGetControllerName (\r
- IN EFI_COMPONENT_NAME2_PROTOCOL *Cnp,\r
- IN EFI_HANDLE ControllerHandle,\r
- IN EFI_HANDLE ChildHandle OPTIONAL,\r
- IN CHAR8 *Lang,\r
- OUT CHAR16 **ControllerName\r
- );\r
-\r
-/*------------------------------------------------------------------------------\r
- Utility functions\r
-------------------------------------------------------------------------------*/\r
-\r
-EFI_MAC_ADDRESS\r
-GetCurrentMacAddress (\r
- VOID\r
- );\r
-\r
-#endif // __LAN9118_DXE_H__\r
+++ /dev/null
-#/** @file\r
-# INF file for the LAN9118 Network Controller Driver.\r
-#\r
-# Copyright (c) 2012-2015, ARM Limited. All rights reserved.\r
-#\r
-# SPDX-License-Identifier: BSD-2-Clause-Patent\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010006\r
- BASE_NAME = Lan9118Dxe\r
- FILE_GUID = 4356b162-d0b2-11e1-8952-4437e6a60ea5\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 0.1\r
- ENTRY_POINT = Lan9118DxeEntry\r
-\r
-[Sources.common]\r
- Lan9118Dxe.c\r
- Lan9118DxeUtil.c\r
- Lan9118Dxe.h\r
-\r
-[Packages]\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- NetworkPkg/NetworkPkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- UefiLib\r
- NetLib\r
- UefiDriverEntryPoint\r
- BaseMemoryLib\r
- IoLib\r
- DevicePathLib\r
-\r
-[Protocols]\r
- gEfiSimpleNetworkProtocolGuid\r
- gEfiMetronomeArchProtocolGuid\r
- gEfiPxeBaseCodeProtocolGuid\r
- gEfiDevicePathProtocolGuid\r
-\r
-[FixedPcd]\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout\r
- gEmbeddedTokenSpaceGuid.PcdLan9118NegotiationFeatureMask\r
-\r
-[Depex]\r
- TRUE\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#ifndef __LAN9118_DXE_HW_H__\r
-#define __LAN9118_DXE_HW_H__\r
-\r
-/*------------------------------------------------------------------------------\r
- LAN9118 SMCS Registers\r
-------------------------------------------------------------------------------*/\r
-\r
-// Base address as on the VE board\r
-#define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))\r
-\r
-/* ------------- Tx and Rx Data and Status Memory Locations ------------------*/\r
-#define LAN9118_RX_DATA (0x00000000 + LAN9118_BA)\r
-#define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA)\r
-#define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA)\r
-#define LAN9118_TX_DATA (0x00000020 + LAN9118_BA)\r
-#define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA)\r
-#define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA)\r
-\r
-/* ------------- System Control and Status Registers -------------------------*/\r
-#define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision\r
-#define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration\r
-#define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status\r
-#define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable\r
-//#define LAN9118_RESERVED (0x00000060)\r
-#define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test\r
-#define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts\r
-#define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration\r
-#define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration\r
-#define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration\r
-#define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration\r
-#define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information\r
-#define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information\r
-#define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control\r
-#define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration\r
-#define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration\r
-#define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count\r
-#define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control\r
-#define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter\r
-#define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter\r
-#define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command\r
-#define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data\r
-#define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration\r
-#define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command\r
-#define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data\r
-\r
-/*\r
- * Required delays following write cycles (number of BYTE_TEST reads)\r
- * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
- * Where no delay listed, 0 has been assumed.\r
- */\r
-#define LAN9118_RX_DATA_WR_DELAY 0\r
-#define LAN9118_RX_STATUS_WR_DELAY 0\r
-#define LAN9118_RX_STATUS_PEEK_WR_DELAY 0\r
-#define LAN9118_TX_DATA_WR_DELAY 0\r
-#define LAN9118_TX_STATUS_WR_DELAY 0\r
-#define LAN9118_TX_STATUS_PEEK_WR_DELAY 0\r
-#define LAN9118_ID_REV_WR_DELAY 0\r
-#define LAN9118_IRQ_CFG_WR_DELAY 3\r
-#define LAN9118_INT_STS_WR_DELAY 2\r
-#define LAN9118_INT_EN_WR_DELAY 1\r
-#define LAN9118_BYTE_TEST_WR_DELAY 0\r
-#define LAN9118_FIFO_INT_WR_DELAY 1\r
-#define LAN9118_RX_CFG_WR_DELAY 1\r
-#define LAN9118_TX_CFG_WR_DELAY 1\r
-#define LAN9118_HW_CFG_WR_DELAY 1\r
-#define LAN9118_RX_DP_CTL_WR_DELAY 1\r
-#define LAN9118_RX_FIFO_INF_WR_DELAY 0\r
-#define LAN9118_TX_FIFO_INF_WR_DELAY 3\r
-#define LAN9118_PMT_CTRL_WR_DELAY 7\r
-#define LAN9118_GPIO_CFG_WR_DELAY 1\r
-#define LAN9118_GPT_CFG_WR_DELAY 1\r
-#define LAN9118_GPT_CNT_WR_DELAY 3\r
-#define LAN9118_WORD_SWAP_WR_DELAY 1\r
-#define LAN9118_FREE_RUN_WR_DELAY 4\r
-#define LAN9118_RX_DROP_WR_DELAY 0\r
-#define LAN9118_MAC_CSR_CMD_WR_DELAY 1\r
-#define LAN9118_MAC_CSR_DATA_WR_DELAY 1\r
-#define LAN9118_AFC_CFG_WR_DELAY 1\r
-#define LAN9118_E2P_CMD_WR_DELAY 1\r
-#define LAN9118_E2P_DATA_WR_DELAY 1\r
-\r
-/*\r
- * Required delays following read cycles (number of BYTE_TEST reads)\r
- * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
- * Where no delay listed, 0 has been assumed.\r
- */\r
-#define LAN9118_RX_DATA_RD_DELAY 3\r
-#define LAN9118_RX_STATUS_RD_DELAY 3\r
-#define LAN9118_RX_STATUS_PEEK_RD_DELAY 0\r
-#define LAN9118_TX_DATA_RD_DELAY 0\r
-#define LAN9118_TX_STATUS_RD_DELAY 3\r
-#define LAN9118_TX_STATUS_PEEK_RD_DELAY 0\r
-#define LAN9118_ID_REV_RD_DELAY 0\r
-#define LAN9118_IRQ_CFG_RD_DELAY 0\r
-#define LAN9118_INT_STS_RD_DELAY 0\r
-#define LAN9118_INT_EN_RD_DELAY 0\r
-#define LAN9118_BYTE_TEST_RD_DELAY 0\r
-#define LAN9118_FIFO_INT_RD_DELAY 0\r
-#define LAN9118_RX_CFG_RD_DELAY 0\r
-#define LAN9118_TX_CFG_RD_DELAY 0\r
-#define LAN9118_HW_CFG_RD_DELAY 0\r
-#define LAN9118_RX_DP_CTL_RD_DELAY 0\r
-#define LAN9118_RX_FIFO_INF_RD_DELAY 0\r
-#define LAN9118_TX_FIFO_INF_RD_DELAY 0\r
-#define LAN9118_PMT_CTRL_RD_DELAY 0\r
-#define LAN9118_GPIO_CFG_RD_DELAY 0\r
-#define LAN9118_GPT_CFG_RD_DELAY 0\r
-#define LAN9118_GPT_CNT_RD_DELAY 0\r
-#define LAN9118_WORD_SWAP_RD_DELAY 0\r
-#define LAN9118_FREE_RUN_RD_DELAY 0\r
-#define LAN9118_RX_DROP_RD_DELAY 4\r
-#define LAN9118_MAC_CSR_CMD_RD_DELAY 0\r
-#define LAN9118_MAC_CSR_DATA_RD_DELAY 0\r
-#define LAN9118_AFC_CFG_RD_DELAY 0\r
-#define LAN9118_E2P_CMD_RD_DELAY 0\r
-#define LAN9118_E2P_DATA_RD_DELAY 0\r
-\r
-// Receiver Status bits\r
-#define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error\r
-#define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits\r
-#define RXSTATUS_MII_ERROR BIT3 // Receive error during interception\r
-#define RXSTATUS_RXW_TO BIT4 // Incoming frame larger than 2kb\r
-#define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame\r
-#define RXSTATUS_LCOLL BIT6 // Late collision detected\r
-#define RXSTATUS_FTL BIT7 // Frame longer than Ether type\r
-#define RXSTATUS_MCF BIT10 // Frame has Multicast Address\r
-#define RXSTATUS_RUNT BIT11 // Bad frame\r
-#define RXSTATUS_LE BIT12 // Actual length of frame different than it claims\r
-#define RXSTATUS_BCF BIT13 // Frame has Broadcast Address\r
-#define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11\r
-#define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask\r
-#define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask\r
-#define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test\r
-\r
-// Transmitter Status bits\r
-#define TXSTATUS_DEF BIT0 // Packet tx was deferred\r
-#define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times)\r
-#define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask\r
-#define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)\r
-#define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes\r
-#define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?)\r
-#define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx\r
-#define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11\r
-#define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)\r
-\r
-// ID_REV register bits\r
-#define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r
-#define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r
-\r
-// Interrupt Config Register bits\r
-#define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type\r
-#define IRQCFG_IRQ_POL BIT4 // IRQ Polarity\r
-#define IRQCFG_IRQ_EN BIT8 // Enable external interrupt\r
-#define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line\r
-#define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval\r
-#define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter\r
-#define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask\r
-\r
-// Interrupt Status Register bits\r
-#define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask\r
-#define INSTS_RSFL (0x8) // Rx Status FIFO Level reached\r
-#define INSTS_RSFF BIT4 // Rx Status FIFO full\r
-#define INSTS_RXDF_INT BIT6 // Rx Frame dropped\r
-#define INSTS_TSFL BIT7 // Tx Status FIFO Level reached\r
-#define INSTS_TSFF BIT8 // Tx Status FIFO full\r
-#define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded\r
-#define INSTS_TDFO BIT10 // Tx Data FIFO full\r
-#define INSTS_TXE BIT13 // Transmitter Error\r
-#define INSTS_RXE BIT14 // Receiver Error\r
-#define INSTS_RWT BIT15 // Packet > 2048 bytes received\r
-#define INSTS_TXSO BIT16 // Tx Status FIFO Overflow\r
-#define INSTS_PME_INT BIT17 // PME Signal detected\r
-#define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt\r
-#define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF\r
-#define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared\r
-#define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO\r
-#define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF\r
-#define INSTS_RXSTOP_INT BIT24 // Rx was stopped\r
-#define INSTS_TXSTOP_INT BIT25 // Tx was stopped\r
-#define INSTS_SW_INT BIT31 // Software Interrupt occurred\r
-\r
-// Interrupt Enable Register bits\r
-\r
-\r
-// Hardware Config Register bits\r
-#define HWCFG_SRST BIT0 // Software Reset bit (SC)\r
-#define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)\r
-#define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO)\r
-#define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size\r
-#define HWCFG_MBO BIT20 // Must Be One bit\r
-\r
-// Power Management Control Register\r
-#define MPTCTRL_READY BIT0 // Device ready indicator\r
-#define MPTCTRL_PME_EN BIT1 // Enable external PME signals\r
-#define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals\r
-#define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)\r
-#define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask\r
-#define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull)\r
-#define MPTCTRL_ED_EN BIT8 // Energy-detect enable\r
-#define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan\r
-#define MPTCTRL_PHY_RST BIT10 // Reset the PHY\r
-#define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode\r
-\r
-// PHY control register bits\r
-#define PHYCR_COLL_TEST BIT7 // Collision test enable\r
-#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r
-#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r
-#define PHYCR_PD BIT11 // Power-Down switch\r
-#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r
-#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r
-#define PHYCR_LOOPBK BIT14 // Set loopback mode\r
-#define PHYCR_RESET BIT15 // Do a PHY reset\r
-\r
-// PHY status register bits\r
-#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r
-#define PHYSTS_JABBER BIT1 // Jabber condition detected\r
-#define PHYSTS_LINK_STS BIT2 // Link Status\r
-#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r
-#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r
-#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r
-#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r
-#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r
-#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r
-#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r
-#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r
-\r
-// PHY Auto-Negotiation advertisement\r
-#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r
-#define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r
-#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r
-#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r
-#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r
-#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r
-#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r
-\r
-\r
-// PHY Auto-Negotiation Link Partner Ability\r
-\r
-// PHY Auto-Negotiation Expansion\r
-\r
-// PHY Mode control/status\r
-\r
-// PHY Special Modes\r
-\r
-// PHY Special control/status\r
-\r
-// PHY Interrupt Source Flags\r
-\r
-// PHY Interrupt Mask\r
-\r
-// PHY Super Special control/status\r
-#define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication\r
-#define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done\r
-\r
-\r
-// MAC control register bits\r
-#define MACCR_RX_EN BIT2 // Enable Receiver bit\r
-#define MACCR_TX_EN BIT3 // Enable Transmitter bit\r
-#define MACCR_DFCHK BIT5 // Deferral Check bit\r
-#define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit\r
-#define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask\r
-#define MACCR_DISRTY BIT10 // Disable Transmit Retry bit\r
-#define MACCR_BCAST BIT11 // Disable Broadcast Frames bit\r
-#define MACCR_LCOLL BIT12 // Late Collision Control bit\r
-#define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit\r
-#define MACCR_HO BIT15 // Hash Only Filtering Mode\r
-#define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit\r
-#define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit\r
-#define MACCR_PRMS BIT18 // Promiscuous Mode bit\r
-#define MACCR_MCPAS BIT19 // Pass all Multicast packets bit\r
-#define MACCR_FDPX BIT20 // Full Duplex Mode bit\r
-#define MACCR_LOOPBK BIT21 // Loopback operation mode bit\r
-#define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit\r
-#define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter\r
-\r
-// Wake-Up Control and Status Register\r
-#define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)\r
-#define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames\r
-#define WUCSR_MPR_MASK (0x10) // Received Magic Packet\r
-#define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame\r
-#define WUCSR_GUE BIT9 // Enable wake on global unicast frames\r
-\r
-// RX Configuration Register bits\r
-#define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes\r
-#define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs\r
-#define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO\r
-#define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO\r
-#define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve\r
-\r
-// TX Configuration Register bits\r
-#define TXCFG_STOP_TX BIT0 // Stop the transmitter\r
-#define TXCFG_TX_ON BIT1 // Start the transmitter\r
-#define TXCFG_TXSAO BIT2 // Tx Status FIFO full\r
-#define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO\r
-#define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO\r
-\r
-// Rx FIFO Information Register bits\r
-#define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space\r
-#define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space\r
-\r
-// Tx FIFO Information Register bits\r
-#define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space\r
-#define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space\r
-\r
-// E2P Register\r
-#define E2P_EPC_BUSY BIT31\r
-#define E2P_EPC_CMD_READ (0)\r
-#define E2P_EPC_TIMEOUT BIT9\r
-#define E2P_EPC_MAC_ADDRESS_LOADED BIT8\r
-#define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF)\r
-\r
-// GPIO Configuration register\r
-#define GPIO_GPIO0_PUSH_PULL BIT16\r
-#define GPIO_GPIO1_PUSH_PULL BIT17\r
-#define GPIO_GPIO2_PUSH_PULL BIT18\r
-#define GPIO_LED1_ENABLE BIT28\r
-#define GPIO_LED2_ENABLE BIT29\r
-#define GPIO_LED3_ENABLE BIT30\r
-\r
-// MII_ACC bits\r
-#define MII_ACC_MII_BUSY BIT0\r
-#define MII_ACC_MII_WRITE BIT1\r
-#define MII_ACC_MII_READ 0\r
-\r
-#define MII_ACC_PHY_VALUE BIT11\r
-#define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6)\r
-\r
-//\r
-// PHY Control Indexes\r
-//\r
-#define PHY_INDEX_BASIC_CTRL 0\r
-#define PHY_INDEX_BASIC_STATUS 1\r
-#define PHY_INDEX_ID1 2\r
-#define PHY_INDEX_ID2 3\r
-#define PHY_INDEX_AUTO_NEG_ADVERT 4\r
-#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r
-#define PHY_INDEX_AUTO_NEG_EXP 6\r
-#define PHY_INDEX_MODE 17\r
-#define PHY_INDEX_SPECIAL_MODES 18\r
-#define PHY_INDEX_SPECIAL_CTLR 27\r
-#define PHY_INDEX_INT_SRC 29\r
-#define PHY_INDEX_INT_MASK 30\r
-#define PHY_INDEX_SPECIAL_PHY_CTLR 31\r
-\r
-// Indirect MAC Indexes\r
-#define INDIRECT_MAC_INDEX_CR 1\r
-#define INDIRECT_MAC_INDEX_ADDRH 2\r
-#define INDIRECT_MAC_INDEX_ADDRL 3\r
-#define INDIRECT_MAC_INDEX_HASHH 4\r
-#define INDIRECT_MAC_INDEX_HASHL 5\r
-#define INDIRECT_MAC_INDEX_MII_ACC 6\r
-#define INDIRECT_MAC_INDEX_MII_DATA 7\r
-\r
-//\r
-// MAC CSR Synchronizer Command register\r
-//\r
-#define MAC_CSR_BUSY BIT31\r
-#define MAC_CSR_READ BIT30\r
-#define MAC_CSR_WRITE 0\r
-#define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF)\r
-\r
-//\r
-// TX Packet Format\r
-//\r
-#define TX_CMD_A_COMPLETION_INT BIT31\r
-#define TX_CMD_A_FIRST_SEGMENT BIT13\r
-#define TX_CMD_A_LAST_SEGMENT BIT12\r
-#define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF)\r
-#define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16)\r
-#define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF)\r
-#define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16)\r
-\r
-// Hardware Configuration Register\r
-#define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16)\r
-#define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16)\r
-\r
-// EEPROM Definition\r
-#define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5\r
-\r
-//\r
-// Conditional compilation flags\r
-//\r
-//#define EVAL_PERFORMANCE\r
-\r
-\r
-#endif /* __LAN9118_DXE_HDR_H__ */\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#include "Lan9118Dxe.h"\r
-\r
-STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };\r
-\r
-/**\r
- This internal function reverses bits for 32bit data.\r
-\r
- @param Value The data to be reversed.\r
-\r
- @return Data reversed.\r
-\r
-**/\r
-UINT32\r
-ReverseBits (\r
- UINT32 Value\r
- )\r
-{\r
- UINTN Index;\r
- UINT32 NewValue;\r
-\r
- NewValue = 0;\r
- for (Index = 0; Index < 32; Index++) {\r
- if ((Value & (1 << Index)) != 0) {\r
- NewValue = NewValue | (1 << (31 - Index));\r
- }\r
- }\r
-\r
- return NewValue;\r
-}\r
-\r
-/*\r
-** Create Ethernet CRC\r
-**\r
-** INFO USED:\r
-** 1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check\r
-**\r
-** 2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html\r
-**\r
-** 3: http://en.wikipedia.org/wiki/Computation_of_CRC\r
-*/\r
-UINT32\r
-GenEtherCrc32 (\r
- IN EFI_MAC_ADDRESS *Mac,\r
- IN UINT32 AddrLen\r
- )\r
-{\r
- INT32 Iter;\r
- UINT32 Remainder;\r
- UINT8 *Ptr;\r
-\r
- Iter = 0;\r
- Remainder = 0xFFFFFFFF; // 0xFFFFFFFF is standard seed for Ethernet\r
-\r
- // Convert Mac Address to array of bytes\r
- Ptr = (UINT8*)Mac;\r
-\r
- // Generate the Crc bit-by-bit (LSB first)\r
- while (AddrLen--) {\r
- Remainder ^= *Ptr++;\r
- for (Iter = 0;Iter < 8;Iter++) {\r
- // Check if exponent is set\r
- if (Remainder & 1) {\r
- Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;\r
- } else {\r
- Remainder = (Remainder >> 1) ^ 0;\r
- }\r
- }\r
- }\r
-\r
- // Reverse the bits before returning (to Big Endian)\r
- //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())\r
- return ReverseBits (Remainder);\r
-}\r
-\r
-// Function to read from MAC indirect registers\r
-UINT32\r
-IndirectMACRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 MacCSR;\r
-\r
- // Check index is in the range\r
- ASSERT(Index <= 12);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Set CSR busy bit to ensure read will occur\r
- // Set the R/W bit to indicate we are reading\r
- // Set the index of CSR Address to access desired register\r
- MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r
-\r
- // Write to the register\r
- Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Now read from data register to get read value\r
- return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA);\r
-}\r
-\r
-/*\r
- * LAN9118 chips have special restrictions on some back-to-back Write/Read or\r
- * Read/Read pairs of accesses. After a read or write that changes the state of\r
- * the device, there is a period in which stale values may be returned in\r
- * response to a read. This period is dependent on the registers accessed.\r
- *\r
- * We must delay prior reads by this period. This can either be achieved by\r
- * timer-based delays, or by performing dummy reads of the BYTE_TEST register,\r
- * for which the recommended number of reads is described in the LAN9118 data\r
- * sheet. This is required in addition to any memory barriers.\r
- *\r
- * This function performs a number of dummy reads of the BYTE_TEST register, as\r
- * a building block for the above.\r
- */\r
-VOID\r
-WaitDummyReads (\r
- UINTN Count\r
- )\r
-{\r
- while (Count--)\r
- MmioRead32(LAN9118_BYTE_TEST);\r
-}\r
-\r
-UINT32\r
-Lan9118RawMmioRead32(\r
- UINTN Address,\r
- UINTN Delay\r
- )\r
-{\r
- UINT32 Value;\r
-\r
- Value = MmioRead32(Address);\r
- WaitDummyReads(Delay);\r
- return Value;\r
-}\r
-\r
-UINT32\r
-Lan9118RawMmioWrite32(\r
- UINTN Address,\r
- UINT32 Value,\r
- UINTN Delay\r
- )\r
-{\r
- MmioWrite32(Address, Value);\r
- WaitDummyReads(Delay);\r
- return Value;\r
-}\r
-\r
-// Function to write to MAC indirect registers\r
-UINT32\r
-IndirectMACWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 ValueWritten;\r
- UINT32 MacCSR;\r
-\r
- // Check index is in the range\r
- ASSERT(Index <= 12);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- // Set CSR busy bit to ensure read will occur\r
- // Set the R/W bit to indicate we are writing\r
- // Set the index of CSR Address to access desired register\r
- MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r
-\r
- // Now write the value to the register before issuing the write command\r
- ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
-\r
- // Write the config to the register\r
- Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
-\r
- // Wait until CSR busy bit is cleared\r
- while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-// Function to read from MII register (PHY Access)\r
-UINT32\r
-IndirectPHYRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 ValueRead;\r
- UINT32 MiiAcc;\r
-\r
- // Check it is a valid index\r
- ASSERT(Index < 31);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Clear the R/W bit to indicate we are reading\r
- // Set the index of the MII register\r
- // Set the PHY Address\r
- // Set the MII busy bit to allow read\r
- MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
-\r
- // Now write this config to register\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Now read the value of the register\r
- ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register\r
-\r
- return ValueRead;\r
-}\r
-\r
-\r
-// Function to write to the MII register (PHY Access)\r
-UINT32\r
-IndirectPHYWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 MiiAcc;\r
- UINT32 ValueWritten;\r
-\r
- // Check it is a valid index\r
- ASSERT(Index < 31);\r
-\r
- // Wait for busy bit to clear\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- // Clear the R/W bit to indicate we are reading\r
- // Set the index of the MII register\r
- // Set the PHY Address\r
- // Set the MII busy bit to allow read\r
- MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
-\r
- // Write the desired value to the register first\r
- ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));\r
-\r
- // Now write the config to register\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
-\r
- // Wait for operation to terminate\r
- while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-\r
-/* ---------------- EEPROM Operations ------------------ */\r
-\r
-\r
-// Function to read from EEPROM memory\r
-UINT32\r
-IndirectEEPROMRead32 (\r
- UINT32 Index\r
- )\r
-{\r
- UINT32 EepromCmd;\r
-\r
- // Set the busy bit to ensure read will occur\r
- EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;\r
-\r
- // Set the index to access desired EEPROM memory location\r
- EepromCmd |= E2P_EPC_ADDRESS(Index);\r
-\r
- // Write to Eeprom command register\r
- Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Check that operation didn't time out\r
- if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r
- return 0;\r
- }\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Finally read the value\r
- return Lan9118MmioRead32 (LAN9118_E2P_DATA);\r
-}\r
-\r
-// Function to write to EEPROM memory\r
-UINT32\r
-IndirectEEPROMWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- )\r
-{\r
- UINT32 ValueWritten;\r
- UINT32 EepromCmd;\r
-\r
- ValueWritten = 0;\r
-\r
- // Read the EEPROM Command register\r
- EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD);\r
-\r
- // Set the busy bit to ensure read will occur\r
- EepromCmd |= ((UINT32)1 << 31);\r
-\r
- // Set the EEPROM command to write(0b011)\r
- EepromCmd &= ~(7 << 28); // Clear the command first\r
- EepromCmd |= (3 << 28); // Write 011\r
-\r
- // Set the index to access desired EEPROM memory location\r
- EepromCmd |= (Index & 0xF);\r
-\r
- // Write the value to the data register first\r
- ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value);\r
-\r
- // Write to Eeprom command register\r
- Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Check that operation didn't time out\r
- if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r
- return 0;\r
- }\r
-\r
- // Wait until operation has completed\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- return ValueWritten;\r
-}\r
-\r
-/* ---------------- General Operations ----------------- */\r
-\r
-VOID\r
-Lan9118SetMacAddress (\r
- EFI_MAC_ADDRESS *Mac,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,\r
- (Mac->Addr[0] & 0xFF) |\r
- ((Mac->Addr[1] & 0xFF) << 8) |\r
- ((Mac->Addr[2] & 0xFF) << 16) |\r
- ((Mac->Addr[3] & 0xFF) << 24)\r
- );\r
-\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,\r
- (UINT32)(Mac->Addr[4] & 0xFF) |\r
- ((Mac->Addr[5] & 0xFF) << 8)\r
- );\r
-}\r
-\r
-VOID\r
-Lan9118ReadMacAddress (\r
- OUT EFI_MAC_ADDRESS *MacAddress\r
- )\r
-{\r
- UINT32 MacAddrHighValue;\r
- UINT32 MacAddrLowValue;\r
-\r
- // Read the Mac Addr high register\r
- MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);\r
- // Read the Mac Addr low register\r
- MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);\r
-\r
- SetMem (MacAddress, sizeof(*MacAddress), 0);\r
- MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);\r
- MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;\r
- MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;\r
- MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;\r
- MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);\r
- MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;\r
-}\r
-\r
-/*\r
- * Power up the 9118 and find its MAC address.\r
- *\r
- * This operation can be carried out when the LAN9118 is in any power state\r
- *\r
- */\r
-EFI_STATUS\r
-Lan9118Initialize (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINTN Retries;\r
- UINT64 DefaultMacAddress;\r
-\r
- // Attempt to wake-up the device if it is in a lower power state\r
- if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
- DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
- Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
- }\r
-\r
- // Check that device is active\r
- Retries = 20;\r
- while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- if (!Retries) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- Retries = 20;\r
- while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- if (!Retries) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- // Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r
- // current address.\r
- if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
- DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r
-\r
- // If we had an address before (set by StationAddress), continue to use it\r
- if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {\r
- Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);\r
- } else {\r
- // If there are no cached addresses, then fall back to a default\r
- DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r
- DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r
- Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r
- CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r
- }\r
- } else {\r
- // Store the MAC address that was loaded from EEPROM\r
- Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);\r
- CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);\r
- }\r
-\r
- // Clear and acknowledge interrupts\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
-\r
- // Do self tests here?\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Perform software reset on the LAN9118\r
-// Return 0 on success, -1 on error\r
-EFI_STATUS\r
-SoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 HwConf;\r
- UINT32 ResetTime;\r
-\r
- // Initialize variable\r
- ResetTime = 0;\r
-\r
- // Stop Rx and Tx\r
- StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);\r
- StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r
-\r
- // Issue the reset\r
- HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
- HwConf |= 1;\r
-\r
- // Set the Must Be One (MBO) bit\r
- if (((HwConf & HWCFG_MBO) >> 20) == 0) {\r
- HwConf |= HWCFG_MBO;\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // Write the configuration\r
- Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
-\r
- // Wait for reset to complete\r
- while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
-\r
- gBS->Stall (LAN9118_STALL);\r
- ResetTime += 1;\r
-\r
- // If time taken exceeds 100us, then there was an error condition\r
- if (ResetTime > 1000) {\r
- Snp->Mode->State = EfiSimpleNetworkStopped;\r
- return EFI_TIMEOUT;\r
- }\r
- }\r
-\r
- // Check that EEPROM isn't active\r
- while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
-\r
- // TODO we probably need to re-set the mac address here.\r
-\r
- // Clear and acknowledge all interrupts\r
- if (Flags & SOFT_RESET_CLEAR_INT) {\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
- }\r
-\r
- // Do self tests here?\r
- if (Flags & SOFT_RESET_SELF_TEST) {\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Perform PHY software reset\r
-EFI_STATUS\r
-PhySoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 PmtCtrl = 0;\r
-\r
- // PMT PHY reset takes precedence over BCR\r
- if (Flags & PHY_RESET_PMT) {\r
- PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
- PmtCtrl |= MPTCTRL_PHY_RST;\r
- Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
-\r
- // Wait for completion\r
- while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- // PHY Basic Control Register reset\r
- } else if (Flags & PHY_RESET_BCR) {\r
- IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r
-\r
- // Wait for completion\r
- while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- }\r
-\r
- // Clear and acknowledge all interrupts\r
- if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r
- Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
- Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-// Configure hardware for LAN9118\r
-EFI_STATUS\r
-ConfigureHardware (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 GpioConf;\r
-\r
- // Check if we want to use LEDs on GPIO\r
- if (Flags & HW_CONF_USE_LEDS) {\r
- GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG);\r
-\r
- // Enable GPIO as LEDs and Config as Push-Pull driver\r
- GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r
- GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r
-\r
- // Write the configuration\r
- Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Configure flow control\r
-EFI_STATUS\r
-ConfigureFlow (\r
- UINT32 Flags,\r
- UINT32 HighTrig,\r
- UINT32 LowTrig,\r
- UINT32 BPDuration,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Do auto-negotiation\r
-EFI_STATUS\r
-AutoNegotiate (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 PhyControl;\r
- UINT32 PhyStatus;\r
- UINT32 Features;\r
- UINT32 Retries;\r
-\r
- // First check that auto-negotiation is supported\r
- PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
- if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {\r
- DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Check that link is up first\r
- if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r
- // Wait until it is up or until Time Out\r
- Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r
- while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
- gBS->Stall (LAN9118_STALL);\r
- Retries--;\r
- if (!Retries) {\r
- DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));\r
- return EFI_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- // Configure features to advertise\r
- Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);\r
-\r
- if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {\r
- // Link speed capabilities\r
- Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);\r
-\r
- // Pause frame capabilities\r
- Features &= ~(PHYANA_PAUSE_OP_MASK);\r
- Features |= 3 << 10;\r
- }\r
- Features &= FixedPcdGet32 (PcdLan9118NegotiationFeatureMask);\r
-\r
- // Write the features\r
- IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);\r
-\r
- // Read control register\r
- PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);\r
-\r
- // Enable Auto-Negotiation\r
- if ((PhyControl & PHYCR_AUTO_EN) == 0) {\r
- PhyControl |= PHYCR_AUTO_EN;\r
- }\r
-\r
- // Restart auto-negotiation\r
- PhyControl |= PHYCR_RST_AUTO;\r
-\r
- // Enable collision test if required to do so\r
- if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {\r
- PhyControl |= PHYCR_COLL_TEST;\r
- } else {\r
- PhyControl &= ~ PHYCR_COLL_TEST;\r
- }\r
-\r
- // Write this configuration\r
- IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);\r
-\r
- // Wait until process has completed\r
- while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Check the Link Status and take appropriate action\r
-EFI_STATUS\r
-CheckLinkStatus (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- // Get the PHY Status\r
- UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
-\r
- if (PhyBStatus & PHYSTS_LINK_STS) {\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_DEVICE_ERROR;\r
- }\r
-}\r
-\r
-// Stop the transmitter\r
-EFI_STATUS\r
-StopTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 TxCfg;\r
-\r
- MacCsr = 0;\r
- TxCfg = 0;\r
-\r
- // Check if we want to clear tx\r
- if (Flags & STOP_TX_CLEAR) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
-\r
- // Check if already stopped\r
- if (Flags & STOP_TX_MAC) {\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if (MacCsr & MACCR_TX_EN) {\r
- MacCsr &= ~MACCR_TX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
- }\r
-\r
- if (Flags & STOP_TX_CFG) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
-\r
- if (TxCfg & TXCFG_TX_ON) {\r
- TxCfg |= TXCFG_STOP_TX;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
-\r
- // Wait for Tx to finish transmitting\r
- while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Stop the receiver\r
-EFI_STATUS\r
-StopRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 RxCfg;\r
-\r
- RxCfg = 0;\r
-\r
- // Check if already stopped\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if (MacCsr & MACCR_RX_EN) {\r
- MacCsr &= ~ MACCR_RX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
-\r
- // Check if we want to clear receiver FIFOs\r
- if (Flags & STOP_RX_CLEAR) {\r
- RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
- RxCfg |= RXCFG_RX_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
-\r
- while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Start the transmitter\r
-EFI_STATUS\r
-StartTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 TxCfg;\r
-\r
- MacCsr = 0;\r
- TxCfg = 0;\r
-\r
- // Check if we want to clear tx\r
- if (Flags & START_TX_CLEAR) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
-\r
- // Check if tx was started from MAC and enable if not\r
- if (Flags & START_TX_MAC) {\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- if ((MacCsr & MACCR_TX_EN) == 0) {\r
- MacCsr |= MACCR_TX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
- }\r
-\r
- // Check if tx was started from TX_CFG and enable if not\r
- if (Flags & START_TX_CFG) {\r
- TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
- if ((TxCfg & TXCFG_TX_ON) == 0) {\r
- TxCfg |= TXCFG_TX_ON;\r
- Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- }\r
- }\r
-\r
- // Set the tx data trigger level\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Start the receiver\r
-EFI_STATUS\r
-StartRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 MacCsr;\r
- UINT32 RxCfg;\r
-\r
- RxCfg = 0;\r
-\r
- // Check if already started\r
- MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
-\r
- if ((MacCsr & MACCR_RX_EN) == 0) {\r
- // Check if we want to clear receiver FIFOs before starting\r
- if (Flags & START_RX_CLEAR) {\r
- RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
- RxCfg |= RXCFG_RX_DUMP;\r
- Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
-\r
- while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
- }\r
-\r
- MacCsr |= MACCR_RX_EN;\r
- IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-// Check Tx Data available space\r
-UINT32\r
-TxDataFreeSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 TxInf;\r
- UINT32 FreeSpace;\r
-\r
- // Get the amount of free space from information register\r
- TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
- FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r
-\r
- return FreeSpace; // Value in bytes\r
-}\r
-\r
-// Check Tx Status used space\r
-UINT32\r
-TxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 TxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
- UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r
-\r
- return UsedSpace << 2; // Value in bytes\r
-}\r
-\r
-// Check Rx Data used space\r
-UINT32\r
-RxDataUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 RxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
- UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r
-\r
- return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r
-}\r
-\r
-// Check Rx Status used space\r
-UINT32\r
-RxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 RxInf;\r
- UINT32 UsedSpace;\r
-\r
- // Get the amount of used space from information register\r
- RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
- UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r
-\r
- return UsedSpace << 2; // Value in bytes\r
-}\r
-\r
-\r
-// Change the allocation of FIFOs\r
-EFI_STATUS\r
-ChangeFifoAllocation (\r
- IN UINT32 Flags,\r
- IN OUT UINTN *TxDataSize OPTIONAL,\r
- IN OUT UINTN *RxDataSize OPTIONAL,\r
- IN OUT UINT32 *TxStatusSize OPTIONAL,\r
- IN OUT UINT32 *RxStatusSize OPTIONAL,\r
- IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- )\r
-{\r
- UINT32 HwConf;\r
- UINT32 TxFifoOption;\r
-\r
- // Check that desired sizes don't exceed limits\r
- if (*TxDataSize > TX_FIFO_MAX_SIZE)\r
- return EFI_INVALID_PARAMETER;\r
-\r
-#if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)\r
- if (*RxDataSize > RX_FIFO_MAX_SIZE) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-#endif\r
-\r
- if (Flags & ALLOC_USE_DEFAULT) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- // If we use the FIFOs (always use this first)\r
- if (Flags & ALLOC_USE_FIFOS) {\r
- // Read the current value of allocation\r
- HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
- TxFifoOption = (HwConf >> 16) & 0xF;\r
-\r
- // Choose the correct size (always use larger than requested if possible)\r
- if (*TxDataSize < TX_FIFO_MIN_SIZE) {\r
- *TxDataSize = TX_FIFO_MIN_SIZE;\r
- *RxDataSize = 13440;\r
- *RxStatusSize = 896;\r
- TxFifoOption = 2;\r
- } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {\r
- *TxDataSize = 2560;\r
- *RxDataSize = 12480;\r
- *RxStatusSize = 832;\r
- TxFifoOption = 3;\r
- } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {\r
- *TxDataSize = 3584;\r
- *RxDataSize = 11520;\r
- *RxStatusSize = 768;\r
- TxFifoOption = 4;\r
- } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option\r
- *TxDataSize = 4608;\r
- *RxDataSize = 10560;\r
- *RxStatusSize = 704;\r
- TxFifoOption = 5;\r
- } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {\r
- *TxDataSize = 5632;\r
- *RxDataSize = 9600;\r
- *RxStatusSize = 640;\r
- TxFifoOption = 6;\r
- } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {\r
- *TxDataSize = 6656;\r
- *RxDataSize = 8640;\r
- *RxStatusSize = 576;\r
- TxFifoOption = 7;\r
- } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {\r
- *TxDataSize = 7680;\r
- *RxDataSize = 7680;\r
- *RxStatusSize = 512;\r
- TxFifoOption = 8;\r
- } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {\r
- *TxDataSize = 8704;\r
- *RxDataSize = 6720;\r
- *RxStatusSize = 448;\r
- TxFifoOption = 9;\r
- } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {\r
- *TxDataSize = 9728;\r
- *RxDataSize = 5760;\r
- *RxStatusSize = 384;\r
- TxFifoOption = 10;\r
- } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {\r
- *TxDataSize = 10752;\r
- *RxDataSize = 4800;\r
- *RxStatusSize = 320;\r
- TxFifoOption = 11;\r
- } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {\r
- *TxDataSize = 11776;\r
- *RxDataSize = 3840;\r
- *RxStatusSize = 256;\r
- TxFifoOption = 12;\r
- } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {\r
- *TxDataSize = 12800;\r
- *RxDataSize = 2880;\r
- *RxStatusSize = 192;\r
- TxFifoOption = 13;\r
- } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {\r
- *TxDataSize = 13824;\r
- *RxDataSize = 1920;\r
- *RxStatusSize = 128;\r
- TxFifoOption = 14;\r
- }\r
- } else {\r
- ASSERT(0); // Untested code path\r
- HwConf = 0;\r
- TxFifoOption = 0;\r
- }\r
-\r
- // Do we need DMA?\r
- if (Flags & ALLOC_USE_DMA) {\r
- return EFI_UNSUPPORTED; // Unsupported as of now\r
- }\r
- // Clear and assign the new size option\r
- HwConf &= ~(0xF0000);\r
- HwConf |= ((TxFifoOption & 0xF) << 16);\r
- Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#ifndef __LAN9118_DXE_UTIL_H__\r
-#define __LAN9118_DXE_UTIL_H__\r
-\r
-// Most common CRC32 Polynomial for little endian machines\r
-#define CRC_POLYNOMIAL 0xEDB88320\r
-\r
-/**\r
- This internal function reverses bits for 32bit data.\r
-\r
- @param Value The data to be reversed.\r
-\r
- @return Data reversed.\r
-\r
-**/\r
-UINT32\r
-ReverseBits (\r
- UINT32 Value\r
- );\r
-\r
-// Create an Ethernet CRC\r
-UINT32\r
-GenEtherCrc32 (\r
- IN EFI_MAC_ADDRESS *Mac,\r
- IN UINT32 AddrLen\r
- );\r
-\r
-UINT32\r
-Lan9118RawMmioRead32(\r
- UINTN Address,\r
- UINTN Delay\r
- );\r
-#define Lan9118MmioRead32(a) \\r
- Lan9118RawMmioRead32(a, a ## _RD_DELAY)\r
-\r
-UINT32\r
-Lan9118RawMmioWrite32(\r
- UINTN Address,\r
- UINT32 Value,\r
- UINTN Delay\r
- );\r
-#define Lan9118MmioWrite32(a, v) \\r
- Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY)\r
-\r
-/* ------------------ MAC CSR Access ------------------- */\r
-\r
-// Read from MAC indirect registers\r
-UINT32\r
-IndirectMACRead32 (\r
- UINT32 Index\r
- );\r
-\r
-\r
-// Write to indirect registers\r
-UINT32\r
-IndirectMACWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- );\r
-\r
-\r
-/* --------------- PHY Registers Access ---------------- */\r
-\r
-// Read from MII register (PHY Access)\r
-UINT32\r
-IndirectPHYRead32(\r
- UINT32 Index\r
- );\r
-\r
-\r
-// Write to the MII register (PHY Access)\r
-UINT32\r
-IndirectPHYWrite32(\r
- UINT32 Index,\r
- UINT32 Value\r
- );\r
-\r
-/* ---------------- EEPROM Operations ------------------ */\r
-\r
-// Read from EEPROM memory\r
-UINT32\r
-IndirectEEPROMRead32 (\r
- UINT32 Index\r
- );\r
-\r
-// Write to EEPROM memory\r
-UINT32\r
-IndirectEEPROMWrite32 (\r
- UINT32 Index,\r
- UINT32 Value\r
- );\r
-\r
-/* ---------------- General Operations ----------------- */\r
-\r
-VOID\r
-Lan9118SetMacAddress (\r
- EFI_MAC_ADDRESS *Mac,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Initialise the LAN9118\r
-EFI_STATUS\r
-Lan9118Initialize (\r
- IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Flags for software reset\r
-#define SOFT_RESET_CHECK_MAC_ADDR_LOAD BIT0\r
-#define SOFT_RESET_CLEAR_INT BIT1\r
-#define SOFT_RESET_SELF_TEST BIT2\r
-\r
-// Perform software reset on the LAN9118\r
-EFI_STATUS\r
-SoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Flags for PHY reset\r
-#define PHY_RESET_PMT BIT0\r
-#define PHY_RESET_BCR BIT1\r
-#define PHY_SOFT_RESET_CLEAR_INT BIT2\r
-\r
-// Perform PHY software reset\r
-EFI_STATUS\r
-PhySoftReset (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Flags for Hardware configuration\r
-#define HW_CONF_USE_LEDS BIT0\r
-\r
-// Configure hardware for LAN9118\r
-EFI_STATUS\r
-ConfigureHardware (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Configure flow control\r
-EFI_STATUS\r
-ConfigureFlow (\r
- UINT32 Flags,\r
- UINT32 HighTrig,\r
- UINT32 LowTrig,\r
- UINT32 BPDuration,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Flags for auto negotiation\r
-#define AUTO_NEGOTIATE_COLLISION_TEST BIT0\r
-#define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1\r
-\r
-// Do auto-negotiation\r
-EFI_STATUS\r
-AutoNegotiate (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Check the Link Status and take appropriate action\r
-EFI_STATUS\r
-CheckLinkStatus (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Stop transmitter flags\r
-#define STOP_TX_MAC BIT0\r
-#define STOP_TX_CFG BIT1\r
-#define STOP_TX_CLEAR BIT2\r
-\r
-// Stop the transmitter\r
-EFI_STATUS\r
-StopTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Stop receiver flags\r
-#define STOP_RX_CLEAR BIT0\r
-\r
-// Stop the receiver\r
-EFI_STATUS\r
-StopRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Start transmitter flags\r
-#define START_TX_MAC BIT0\r
-#define START_TX_CFG BIT1\r
-#define START_TX_CLEAR BIT2\r
-\r
-// Start the transmitter\r
-EFI_STATUS\r
-StartTx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Stop receiver flags\r
-#define START_RX_CLEAR BIT0\r
-\r
-// Start the receiver\r
-EFI_STATUS\r
-StartRx (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Check Tx Data available space\r
-UINT32\r
-TxDataFreeSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Check Tx Status used space\r
-UINT32\r
-TxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Check Rx Data used space\r
-UINT32\r
-RxDataUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-// Check Rx Status used space\r
-UINT32\r
-RxStatusUsedSpace (\r
- UINT32 Flags,\r
- EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-\r
-// Flags for FIFO allocation\r
-#define ALLOC_USE_DEFAULT BIT0\r
-#define ALLOC_USE_FIFOS BIT1\r
-#define ALLOC_USE_DMA BIT2\r
-\r
-// FIFO min and max sizes\r
-#define TX_FIFO_MIN_SIZE 0x00000600\r
-#define TX_FIFO_MAX_SIZE 0x00003600\r
-//#define RX_FIFO_MIN_SIZE\r
-//#define RX_FIFO_MAX_SIZE\r
-\r
-// Change the allocation of FIFOs\r
-EFI_STATUS\r
-ChangeFifoAllocation (\r
- IN UINT32 Flags,\r
- IN OUT UINTN *TxDataSize OPTIONAL,\r
- IN OUT UINTN *RxDataSize OPTIONAL,\r
- IN OUT UINT32 *TxStatusSize OPTIONAL,\r
- IN OUT UINT32 *RxStatusSize OPTIONAL,\r
- IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
- );\r
-\r
-VOID\r
-Lan9118ReadMacAddress (\r
- OUT EFI_MAC_ADDRESS *Mac\r
- );\r
-\r
-#endif // __LAN9118_DXE_UTIL_H__\r
gEmbeddedTokenSpaceGuid.PcdGdbMaxPacketRetryCount|10000000|UINT32|0x0000004c\r
gEmbeddedTokenSpaceGuid.PcdGdbTimerPeriodMilliseconds|250|UINT32|0x0000004d\r
\r
- # LAN9118 Ethernet Driver PCDs\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x0|UINT32|0x00000025\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x0|UINT64|0x00000026\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|4000|UINT32|0x00000027\r
- # The default feature mask below disables full duplex negotiation, since full\r
- # duplex operation is suspected to be broken in the driver.\r
- gEmbeddedTokenSpaceGuid.PcdLan9118NegotiationFeatureMask|0xFFFFFEBF|UINT32|0x00000028\r
-\r
#\r
# Android FastBoot\r
#\r
projects / mirror_edk2.git / commitdiff