ASSERT(Index <= 12);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Set CSR busy bit to ensure read will occur\r
// Set the R/W bit to indicate we are reading\r
MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r
\r
// Write to the register\r
- MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
+ Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Now read from data register to get read value\r
- return MmioRead32 (LAN9118_MAC_CSR_DATA);\r
+ return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA);\r
+}\r
+\r
+/*\r
+ * LAN9118 chips have special restrictions on some back-to-back Write/Read or\r
+ * Read/Read pairs of accesses. After a read or write that changes the state of\r
+ * the device, there is a period in which stale values may be returned in\r
+ * response to a read. This period is dependent on the registers accessed.\r
+ *\r
+ * We must delay prior reads by this period. This can either be achieved by\r
+ * timer-based delays, or by performing dummy reads of the BYTE_TEST register,\r
+ * for which the recommended number of reads is described in the LAN9118 data\r
+ * sheet. This is required in addition to any memory barriers.\r
+ *\r
+ * This function performs a number of dummy reads of the BYTE_TEST register, as\r
+ * a building block for the above.\r
+ */\r
+VOID\r
+WaitDummyReads (\r
+ UINTN Count\r
+ )\r
+{\r
+ while (Count--)\r
+ MmioRead32(LAN9118_BYTE_TEST);\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioRead32(\r
+ UINTN Address,\r
+ UINTN Delay\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ Value = MmioRead32(Address);\r
+ WaitDummyReads(Delay);\r
+ return Value;\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioWrite32(\r
+ UINTN Address,\r
+ UINT32 Value,\r
+ UINTN Delay\r
+ )\r
+{\r
+ MmioWrite32(Address, Value);\r
+ WaitDummyReads(Delay);\r
+ return Value;\r
}\r
\r
// Function to write to MAC indirect registers\r
ASSERT(Index <= 12);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Set CSR busy bit to ensure read will occur\r
// Set the R/W bit to indicate we are writing\r
MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r
\r
// Now write the value to the register before issuing the write command\r
- ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
+ ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
\r
// Write the config to the register\r
- MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
+ Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
return ValueWritten;\r
}\r
EepromCmd |= E2P_EPC_ADDRESS(Index);\r
\r
// Write to Eeprom command register\r
- MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Check that operation didn't time out\r
- if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
+ if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r
return 0;\r
}\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Finally read the value\r
- return MmioRead32 (LAN9118_E2P_DATA);\r
+ return Lan9118MmioRead32 (LAN9118_E2P_DATA);\r
}\r
\r
// Function to write to EEPROM memory\r
ValueWritten = 0;\r
\r
// Read the EEPROM Command register\r
- EepromCmd = MmioRead32 (LAN9118_E2P_CMD);\r
+ EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD);\r
\r
// Set the busy bit to ensure read will occur\r
EepromCmd |= ((UINT32)1 << 31);\r
EepromCmd |= (Index & 0xF);\r
\r
// Write the value to the data register first\r
- ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);\r
+ ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value);\r
\r
// Write to Eeprom command register\r
- MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Check that operation didn't time out\r
- if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
+ if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r
return 0;\r
}\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
return ValueWritten;\r
}\r
(UINT32)(Mac->Addr[4] & 0xFF) |\r
((Mac->Addr[5] & 0xFF) << 8)\r
);\r
-\r
- CopyMem (&Snp->Mode->CurrentAddress, &Mac, NET_ETHER_ADDR_LEN);\r
}\r
\r
VOID\r
IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
)\r
{\r
- UINTN Timeout;\r
+ UINTN Retries;\r
UINT64 DefaultMacAddress;\r
\r
// Attempt to wake-up the device if it is in a lower power state\r
- if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
+ if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
- MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
}\r
\r
// Check that device is active\r
- Timeout = 20;\r
- while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Timeout) {\r
+ Retries = 20;\r
+ while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r
gBS->Stall (LAN9118_STALL);\r
}\r
- if (!Timeout) {\r
+ if (!Retries) {\r
return EFI_TIMEOUT;\r
}\r
\r
// Check that EEPROM isn't active\r
- Timeout = 20;\r
- while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Timeout){\r
+ Retries = 20;\r
+ while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r
gBS->Stall (LAN9118_STALL);\r
}\r
- if (!Timeout) {\r
+ if (!Retries) {\r
return EFI_TIMEOUT;\r
}\r
\r
// Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r
// current address.\r
- if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
+ if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r
\r
// If we had an address before (set by StationAddess), continue to use it\r
DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r
DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r
Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r
+ CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r
}\r
} else {\r
// Store the MAC address that was loaded from EEPROM\r
}\r
\r
// Clear and acknowledge interrupts\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
\r
// Do self tests here?\r
\r
StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r
\r
// Issue the reset\r
- HwConf = MmioRead32 (LAN9118_HW_CFG);\r
+ HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
HwConf |= 1;\r
\r
// Set the Must Be One (MBO) bit\r
}\r
\r
// Check that EEPROM isn't active\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Write the configuration\r
- MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
\r
// Wait for reset to complete\r
- while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
+ while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
\r
gBS->Stall (LAN9118_STALL);\r
ResetTime += 1;\r
}\r
\r
// Check that EEPROM isn't active\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// TODO we probably need to re-set the mac address here.\r
\r
// Clear and acknowledge all interrupts\r
if (Flags & SOFT_RESET_CLEAR_INT) {\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
}\r
\r
// Do self tests here?\r
)\r
{\r
UINT32 PmtCtrl = 0;\r
- UINT32 LinkTo = 0;\r
\r
// PMT PHY reset takes precedence over BCR\r
if (Flags & PHY_RESET_PMT) {\r
- PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);\r
+ PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
PmtCtrl |= MPTCTRL_PHY_RST;\r
- MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
+ Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
\r
// Wait for completion\r
- while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
+ while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
gBS->Stall (LAN9118_STALL);\r
}\r
// PHY Basic Control Register reset\r
- } else if (Flags & PHY_RESET_PMT) {\r
+ } else if (Flags & PHY_RESET_BCR) {\r
IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r
\r
// Wait for completion\r
}\r
}\r
\r
- // Check the link status\r
- if (Flags & PHY_RESET_CHECK_LINK) {\r
- LinkTo = 100000; // 2 second (could be 50% more)\r
- while (EFI_ERROR (CheckLinkStatus (0, Snp)) && (LinkTo > 0)) {\r
- gBS->Stall (LAN9118_STALL);\r
- LinkTo--;\r
- }\r
-\r
- // Timed out\r
- if (LinkTo <= 0) {\r
- return EFI_TIMEOUT;\r
- }\r
- }\r
-\r
// Clear and acknowledge all interrupts\r
if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
}\r
\r
return EFI_SUCCESS;\r
\r
// Check if we want to use LEDs on GPIO\r
if (Flags & HW_CONF_USE_LEDS) {\r
- GpioConf = MmioRead32 (LAN9118_GPIO_CFG);\r
+ GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG);\r
\r
// Enable GPIO as LEDs and Config as Push-Pull driver\r
GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r
GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r
\r
// Write the configuration\r
- MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
}\r
\r
return EFI_SUCCESS;\r
UINT32 PhyControl;\r
UINT32 PhyStatus;\r
UINT32 Features;\r
- UINT32 TimeOut;\r
+ UINT32 Retries;\r
\r
// First check that auto-negotiation is supported\r
PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
// Check that link is up first\r
if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r
// Wait until it is up or until Time Out\r
- TimeOut = 2000;\r
+ Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r
while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
gBS->Stall (LAN9118_STALL);\r
- TimeOut--;\r
- if (!TimeOut) {\r
+ Retries--;\r
+ if (!Retries) {\r
DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));\r
return EFI_TIMEOUT;\r
}\r
Features &= ~(PHYANA_PAUSE_OP_MASK);\r
Features |= 3 << 10;\r
}\r
+ Features &= FixedPcdGet32 (PcdLan9118NegotiationFeatureMask);\r
\r
// Write the features\r
IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);\r
\r
// Check if we want to clear tx\r
if (Flags & STOP_TX_CLEAR) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
\r
// Check if already stopped\r
}\r
\r
if (Flags & STOP_TX_CFG) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
\r
if (TxCfg & TXCFG_TX_ON) {\r
TxCfg |= TXCFG_STOP_TX;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
\r
// Wait for Tx to finish transmitting\r
- while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
+ while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
}\r
}\r
\r
\r
// Check if we want to clear receiver FIFOs\r
if (Flags & STOP_RX_CLEAR) {\r
- RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
+ RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
- MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
\r
- while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
+ while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
\r
return EFI_SUCCESS;\r
\r
// Check if we want to clear tx\r
if (Flags & START_TX_CLEAR) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
\r
// Check if tx was started from MAC and enable if not\r
if (Flags & START_TX_MAC) {\r
MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- gBS->Stall (LAN9118_STALL);\r
if ((MacCsr & MACCR_TX_EN) == 0) {\r
MacCsr |= MACCR_TX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- gBS->Stall (LAN9118_STALL);\r
}\r
}\r
\r
// Check if tx was started from TX_CFG and enable if not\r
if (Flags & START_TX_CFG) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
- gBS->Stall (LAN9118_STALL);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
if ((TxCfg & TXCFG_TX_ON) == 0) {\r
TxCfg |= TXCFG_TX_ON;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
}\r
\r
if ((MacCsr & MACCR_RX_EN) == 0) {\r
// Check if we want to clear receiver FIFOs before starting\r
if (Flags & START_RX_CLEAR) {\r
- RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
+ RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
- MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
\r
- while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
+ while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
\r
MacCsr |= MACCR_RX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- gBS->Stall (LAN9118_STALL);\r
}\r
\r
return EFI_SUCCESS;\r
UINT32 FreeSpace;\r
\r
// Get the amount of free space from information register\r
- TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
+ TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r
\r
return FreeSpace; // Value in bytes\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
+ TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r
\r
return UsedSpace << 2; // Value in bytes\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
+ RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r
\r
return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
+ RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r
\r
return UsedSpace << 2; // Value in bytes\r
// If we use the FIFOs (always use this first)\r
if (Flags & ALLOC_USE_FIFOS) {\r
// Read the current value of allocation\r
- HwConf = MmioRead32 (LAN9118_HW_CFG);\r
+ HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
TxFifoOption = (HwConf >> 16) & 0xF;\r
\r
// Choose the correct size (always use larger than requested if possible)\r
// Clear and assign the new size option\r
HwConf &= ~(0xF0000);\r
HwConf |= ((TxFifoOption & 0xF) << 16);\r
- MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
\r
return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff