/** @file\r
- This module implement Pci register operation interface for \r
- Pci device.\r
- \r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ PCI command register operations supporting functions implementation for PCI Bus module.\r
\r
-**/\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
\r
/**\r
Operate the PCI register via PciIo function interface.\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- @param Command Operator command\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+ @param Command Operator command.\r
@param Offset The address within the PCI configuration space for the PCI controller.\r
- @param Operation Type of Operation\r
- @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r
- \r
- @return status of PciIo operation\r
+ @param Operation Type of Operation.\r
+ @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r
+\r
+ @return Status of PciIo operation.\r
+\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
PciIo = &PciIoDevice->PciIo;\r
\r
if (Operation != EFI_SET_REGISTER) {\r
- Status = PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
\r
if (Operation == EFI_GET_REGISTER) {\r
*PtrCommand = OldCommand;\r
OldCommand = Command;\r
}\r
\r
- return PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ return PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
}\r
\r
/**\r
- check the cpability of this device supports\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- \r
- @retval TRUE Support\r
- @retval FALSE Not support.\r
+ Check the cpability supporting by given device.\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+\r
+ @retval TRUE Cpability supportted.\r
+ @retval FALSE Cpability not supportted.\r
+\r
**/\r
BOOLEAN\r
PciCapabilitySupport (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
-\r
- if (PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) {\r
+ if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {\r
return TRUE;\r
}\r
\r
}\r
\r
/**\r
- Locate cap reg.\r
- \r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param CapId - The cap ID.\r
- @param Offset - A pointer to the offset.\r
- @param NextRegBlock - A pointer to the next block.\r
- \r
- @retval EFI_UNSUPPORTED Pci device does not support\r
+ Locate capability register block per capability ID.\r
+\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param CapId The capability ID.\r
+ @param Offset A pointer to the offset returned.\r
+ @param NextRegBlock A pointer to the next block returned.\r
+\r
+ @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
- @retval EFI_SUCCESS Success to locate capability register block\r
+\r
**/\r
EFI_STATUS\r
LocateCapabilityRegBlock (\r
CapabilityPtr = 0;\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
} else {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
}\r
}\r
\r
- while (CapabilityPtr > 0x3F) {\r
- //\r
- // Mask it to DWORD alignment per PCI spec\r
- //\r
- CapabilityPtr &= 0xFC;\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint16,\r
- CapabilityPtr,\r
- 1,\r
- &CapabilityEntry\r
- );\r
+ while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint16,\r
+ CapabilityPtr,\r
+ 1,\r
+ &CapabilityEntry\r
+ );\r
\r
CapabilityID = (UINT8) CapabilityEntry;\r
\r
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