PciIo = &PciIoDevice->PciIo;\r
\r
if (Operation != EFI_SET_REGISTER) {\r
- Status = PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
\r
if (Operation == EFI_GET_REGISTER) {\r
*PtrCommand = OldCommand;\r
OldCommand = Command;\r
}\r
\r
- return PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ return PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
}\r
\r
/**\r
CapabilityPtr = 0;\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
} else {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
}\r
}\r
\r
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint16,\r
- CapabilityPtr,\r
- 1,\r
- &CapabilityEntry\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint16,\r
+ CapabilityPtr,\r
+ 1,\r
+ &CapabilityEntry\r
+ );\r
\r
CapabilityID = (UINT8) CapabilityEntry;\r
\r