#ifndef _EFI_PCI_LIB_H_\r
#define _EFI_PCI_LIB_H_\r
\r
-//\r
-// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r
-//\r
-#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01\r
-#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02\r
-#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04\r
-#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08\r
-#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x10\r
\r
typedef struct {\r
EFI_HANDLE Handle;\r
**/\r
EFI_STATUS\r
PciHostBridgeEnumerator (\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- );\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoRead (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- If PCI incompatibility check is enabled, do incompatibility check.\r
-\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of PCI configuration operations to perform.\r
- @param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoWrite (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
);\r
\r
#endif\r
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