/** @file\r
+ PCI resouces support functions implemntation for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
**/\r
\r
#include "PciBus.h"\r
-#include "PciResourceSupport.h"\r
-#include "PciCommand.h"\r
\r
/**\r
- The function is used to skip VGA range\r
- \r
- @param Start address including VGA range\r
- @param Length length of VGA range.\r
- \r
- @retval EFI_SUCCESS success.\r
+ The function is used to skip VGA range.\r
+\r
+ @param Start Returned start address including VGA range.\r
+ @param Length The length of VGA range.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipVGAAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
//\r
// For legacy VGA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= VGABASE1) {\r
*Start = *Start - StartOffset + VGALIMIT2 + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to skip ISA aliasing aperture.\r
- \r
- @param Start address including ISA aliasing aperture.\r
- @param Length length of ISA aliasing aperture.\r
- \r
- @retval EFI_SUCCESS success.\r
+\r
+ @param Start Returned start address including ISA aliasing aperture.\r
+ @param Length The length of ISA aliasing aperture.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipIsaAliasAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
+\r
//\r
// For legacy ISA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= ISABASE) {\r
*Start = *Start - StartOffset + ISALIMIT + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
@param Bridge PCI resource node for bridge.\r
@param ResNode Resource node want to be inserted.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InsertResourceNode (\r
- PCI_RESOURCE_NODE *Bridge,\r
- PCI_RESOURCE_NODE *ResNode\r
+ IN PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
)\r
{\r
LIST_ENTRY *CurrentLink;\r
\r
CurrentLink = ResNode->Link.ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
+ This routine is used to merge two different resource trees in need of\r
+ resoure degradation.\r
\r
-Routine Description:\r
-\r
- This routine is used to merge two different resource tree in need of\r
- resoure degradation. For example, if a upstream PPB doesn't support,\r
+ For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
to merge prefectchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
+ If Dst is NULL or Res is NULL, ASSERT ().\r
\r
@param Dst Point to destination resource tree.\r
@param Res Point to source resource tree.\r
- @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of \r
+ @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of\r
destination resource type.\r
- \r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
MergeResourceTree (\r
- PCI_RESOURCE_NODE *Dst,\r
- PCI_RESOURCE_NODE *Res,\r
- BOOLEAN TypeMerge\r
+ IN PCI_RESOURCE_NODE *Dst,\r
+ IN PCI_RESOURCE_NODE *Res,\r
+ IN BOOLEAN TypeMerge\r
)\r
{\r
\r
\r
RemoveEntryList (CurrentLink);\r
InsertResourceNode (Dst, Temp);\r
-\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to calculate the IO16 aperture\r
for a bridge.\r
\r
- @param Bridge PCI resource node for bridge.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resource node for bridge.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateApertureIo16 (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
EFI_STATUS Status;\r
BOOLEAN IsaEnable;\r
BOOLEAN VGAEnable;\r
EFI_PCI_PLATFORM_POLICY PciPolicy;\r
- \r
\r
//\r
// Always assume there is ISA device and VGA device on the platform\r
&PciPolicy\r
);\r
if (!EFI_ERROR (Status)) {\r
- if (PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) {\r
+ if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
IsaEnable = TRUE;\r
}\r
- if (PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) {\r
+ if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
VGAEnable = TRUE;\r
}\r
}\r
Aperture = 0;\r
\r
if (Bridge == NULL) {\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
// If both of them are enabled, then the IO resource would\r
// become too limited to meet the requirement of most of devices.\r
//\r
-\r
if (IsaEnable || VGAEnable) {\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
//\r
if (IsaEnable) {\r
SkipIsaAliasAperture (\r
&Aperture,\r
- Node->Length \r
+ Node->Length\r
);\r
Offset = Aperture & (Node->Alignment);\r
if (Offset != 0) {\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to calculate the resource aperture\r
for a given bridge device.\r
\r
- @param Bridge Give bridge device.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resouce node for given bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateResourceAperture (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
UINT64 Aperture;\r
Aperture = 0;\r
\r
if (Bridge == NULL) {\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
if (Bridge->ResType == PciBarTypeIo16) {\r
- return CalculateApertureIo16 (Bridge);\r
+\r
+ CalculateApertureIo16 (Bridge);\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
//\r
// Apply padding resource if available\r
//\r
- \r
+\r
Offset = Aperture & (Node->Alignment);\r
\r
if (Offset != 0) {\r
//\r
// Consider the aperture alignment\r
//\r
- \r
+\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
\r
if (Bridge->Length < Aperture) {\r
Bridge->Length = Aperture;\r
}\r
- \r
+\r
//\r
// At last, adjust the bridge's alignment to the first child's alignment\r
// if the bridge has at least one child\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Get IO/Memory resource infor for given PCI device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO .\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceFromDevice (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
\r
if (!ResourceRequested) {\r
PciDev->Allocated = TRUE;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
@param Bar Bar index.\r
@param ResType Type of resource: IO/Memory.\r
@param ResUsage Resource usage.\r
+\r
+ @return PCI resource node created for given PCI device.\r
+ NULL means PCI resource node is not created.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
CreateResourceNode (\r
Node->Reserved = FALSE;\r
Node->ResourceUsage = ResUsage;\r
InitializeListHead (&Node->ChildList);\r
+\r
return Node;\r
}\r
\r
/**\r
- This routine is used to extract resource request from\r
+ This function is used to extract resource request from\r
device node list.\r
\r
@param Bridge Pci device instance.\r
@param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
CreateResourceMap (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *IoNode,\r
// Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
// is aligned with 4KB\r
// This device is typically a bridge device like PPB and P2C\r
+ // Note: 0x1000 aligned\r
//\r
IoBridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFF,\r
- PPB_IO_RANGE,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- ); //0x1000 aligned\r
- \r
+ Temp,\r
+ 0,\r
+ 0xFFF,\r
+ PPB_IO_RANGE,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
+\r
Mem32Bridge = CreateResourceNode (\r
Temp,\r
0,\r
);\r
\r
PMem32Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM32_RANGE,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM32_RANGE,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem64Bridge = CreateResourceNode (\r
Temp,\r
);\r
\r
PMem64Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM64_RANGE,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM64_RANGE,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
//\r
// Recursively create resouce map on this bridge\r
CalculateResourceAperture (Mem64Node);\r
CalculateResourceAperture (PMem64Node);\r
CalculateResourceAperture (IoNode);\r
-\r
- return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingPolicy (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
//\r
PMem64Node\r
);\r
}\r
-\r
- return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
- This function is used to degrade resource if the upstream bridge \r
- doesn't support certain resource. Degradation path is \r
+ This function is used to degrade resource if the upstream bridge\r
+ doesn't support certain resource. Degradation path is\r
PMEM64 -> MEM64 -> MEM32\r
PMEM64 -> PMEM32 -> MEM32\r
IO32 -> IO16.\r
\r
@param Bridge Pci device instance.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
DegradeResource (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *Mem32Node,\r
//\r
// For RootBridge, PPB , P2C, go recursively to traverse all its children\r
// to find if this bridge and downstream has OptionRom.\r
- // \r
+ //\r
HasOprom = FALSE;\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
if (Temp->RomSize != 0) {\r
HasOprom = TRUE;\r
break;\r
- } \r
+ }\r
CurrentLink = CurrentLink->ForwardLink;\r
- } \r
+ }\r
\r
//\r
// If bridge doesn't support Prefetchable\r
//\r
// if no PMem32 request and no OptionRom request, still keep PMem64. Otherwise degrade to PMem32\r
//\r
- if ((PMem32Node != NULL && (PMem32Node->Length != 0 && Bridge->Parent != NULL)) || HasOprom) { \r
+ if ((PMem32Node != NULL && (PMem32Node->Length != 0 && Bridge->Parent != NULL)) || HasOprom) {\r
//\r
// Fixed the issue that there is no resource for 64-bit (above 4G)\r
//\r
FALSE\r
);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Test whether bridge device support decode resource\r
- \r
+ Test whether bridge device support decode resource.\r
+\r
@param Bridge Bridge device instance.\r
@param Decode Decode type according to resource type.\r
- \r
- @return TRUE bridge device support decode resource.\r
- @return FALSE bridge device don't support decode resource.\r
- \r
+\r
+ @return TRUE The bridge device support decode resource.\r
+ @return FALSE The bridge device don't support decode resource.\r
+\r
**/\r
BOOLEAN\r
BridgeSupportResourceDecode (\r
IN UINT32 Decode\r
)\r
{\r
-\r
if (((Bridge->Decodes) & Decode) != 0) {\r
return TRUE;\r
}\r
}\r
\r
/**\r
- This function is used to program the resource allocated \r
- for each resource node.\r
-\r
- \r
- @param Base Base address of resource.\r
- @param Bridge Bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ This function is used to program the resource allocated\r
+ for each resource node under specified bridge.\r
+\r
+ @param Base Base address of resource to be progammed.\r
+ @param Bridge PCI resource node for the bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully to program all resouces\r
+ on given PCI bridge device.\r
+ @retval EFI_OUT_OF_RESOURCES Base is all one.\r
+\r
**/\r
EFI_STATUS\r
ProgramResource (\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r
\r
if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
+ //\r
+ // Program the PCI Card Bus device\r
+ //\r
ProgramP2C (Base, Node);\r
} else {\r
+ //\r
+ // Program the PCI device BAR\r
+ //\r
ProgramBar (Base, Node);\r
}\r
} else {\r
+ //\r
+ // Program the PCI devices under this bridge\r
+ //\r
Status = ProgramResource (Base + Node->Offset, Node);\r
-\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
\r
/**\r
- Program Bar register.\r
- \r
- @param Base Base address for resource.\r
+ Program Bar register for PCI device.\r
+\r
+ @param Base Base address for PCI device resource to be progammed.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramBar (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program PPB apperture.\r
- \r
+ Program PCI-PCI bridge apperture.\r
+\r
@param Base Base address for resource.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramPpbApperture (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
\r
Address = 0;\r
//\r
- // if no device south of this PPB, return anyway\r
+ // If no device resource of this PPB, return anyway\r
// Apperture is set default in the initialization code\r
//\r
if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
//\r
// For padding resource node, just ignore when programming\r
//\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
PciIo = &(Node->PciDev->PciIo);\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program parent bridge for oprom.\r
- \r
+ Program parent bridge for Option Rom.\r
+\r
@param PciDevice Pci deivce instance.\r
- @param OptionRomBase Base address for oprom.\r
- @param Enable Enable/Disable.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param OptionRomBase Base address for Optiona Rom.\r
+ @param Enable Enable or disable PCI memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgrameUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
Node.Offset = 0;\r
\r
//\r
- // Program PPB to only open a single <= 16<MB apperture\r
+ // Program PPB to only open a single <= 16MB apperture\r
//\r
if (Enable) {\r
ProgramPpbApperture (OptionRomBase, &Node);\r
\r
Parent = Parent->Parent;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Test whether resource exists for a bridge.\r
- \r
+\r
@param Bridge Point to resource node for a bridge.\r
- \r
- @return whether resource exists.\r
+\r
+ @retval TRUE There is resource on the given bridge.\r
+ @retval FALSE There isn't resource on the given bridge.\r
+\r
**/\r
BOOLEAN\r
ResourceRequestExisted (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
if (Bridge != NULL) {\r
\r
/**\r
Initialize resource pool structure.\r
- \r
- @param ResourcePool Point to resource pool structure.\r
+\r
+ @param ResourcePool Point to resource pool structure. This pool\r
+ is reset to all zero when returned.\r
@param ResourceType Type of resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeResourcePool (\r
- PCI_RESOURCE_NODE *ResourcePool,\r
- PCI_BAR_TYPE ResourceType\r
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,\r
+ IN PCI_BAR_TYPE ResourceType\r
)\r
{\r
-\r
ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r
ResourcePool->ResType = ResourceType;\r
ResourcePool->Signature = PCI_RESOURCE_SIGNATURE;\r
InitializeListHead (&ResourcePool->ChildList);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
+\r
/**\r
Get all resource information for given Pci device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoBridge Io resource node.\r
@param Mem32Bridge 32-bit memory node.\r
@param PMem64Bridge 64-bit PMemory node.\r
@param IoPool Link list header for Io resource.\r
@param Mem32Pool Link list header for 32-bit memory.\r
- @param PMem32Pool Link list header for 32-bit Pmemory.\r
+ @param PMem32Pool Link list header for 32-bit Prefetchable memory.\r
@param Mem64Pool Link list header for 64-bit memory.\r
- @param PMem64Pool Link list header for 64-bit Pmemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Pool Link list header for 64-bit Prefetchable memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceMap (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE **IoBridge,\r
- PCI_RESOURCE_NODE **Mem32Bridge,\r
- PCI_RESOURCE_NODE **PMem32Bridge,\r
- PCI_RESOURCE_NODE **Mem64Bridge,\r
- PCI_RESOURCE_NODE **PMem64Bridge,\r
- PCI_RESOURCE_NODE *IoPool,\r
- PCI_RESOURCE_NODE *Mem32Pool,\r
- PCI_RESOURCE_NODE *PMem32Pool,\r
- PCI_RESOURCE_NODE *Mem64Pool,\r
- PCI_RESOURCE_NODE *PMem64Pool\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE **IoBridge,\r
+ IN PCI_RESOURCE_NODE **Mem32Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem32Bridge,\r
+ IN PCI_RESOURCE_NODE **Mem64Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem64Bridge,\r
+ IN PCI_RESOURCE_NODE *IoPool,\r
+ IN PCI_RESOURCE_NODE *Mem32Pool,\r
+ IN PCI_RESOURCE_NODE *PMem32Pool,\r
+ IN PCI_RESOURCE_NODE *Mem64Pool,\r
+ IN PCI_RESOURCE_NODE *PMem64Pool\r
)\r
{\r
\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Destory given resource tree.\r
- \r
- @param Bridge root node of resource tree.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
+ @param Bridge PCI resource root node of resource tree.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
DestroyResourceTree (\r
IN PCI_RESOURCE_NODE *Bridge\r
)\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+ ASSERT (Temp);\r
\r
RemoveEntryList (CurrentLink);\r
\r
DestroyResourceTree (Temp);\r
}\r
\r
- gBS->FreePool (Temp);\r
+ FreePool (Temp);\r
}\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Record the reserved resource and insert to reserved list.\r
- \r
- @param Base Base address of reserved resourse.\r
- @param Length Length of reserved resource. \r
- @param ResType Resource type.\r
- @param Bridge Pci device instance.\r
-**/\r
-EFI_STATUS\r
-RecordReservedResource (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN PCI_BAR_TYPE ResType,\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-{\r
- PCI_RESERVED_RESOURCE_LIST *ReservedNode;\r
-\r
- ReservedNode = AllocatePool (sizeof (PCI_RESERVED_RESOURCE_LIST));\r
- if (ReservedNode == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- ReservedNode->Signature = RESERVED_RESOURCE_SIGNATURE;\r
- ReservedNode->Node.Base = Base;\r
- ReservedNode->Node.Length = Length;\r
- ReservedNode->Node.ResType = ResType;\r
-\r
- InsertTailList (&Bridge->ReservedResourceList, &(ReservedNode->Link));\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Insert resource padding for P2C.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingForCardBusBridge (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
PCI_RESOURCE_NODE *Node;\r
// Bar 1 denodes memory range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 1,\r
- PciBarTypeMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 1,\r
+ PciBarTypeMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
Mem32Node,\r
// Bar 2 denodes memory range1\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 2,\r
- PciBarTypePMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 2,\r
+ PciBarTypePMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
PMem32Node,\r
// Bar 3 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 3,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 3,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
// Bar 4 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 4,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 4,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
Node\r
);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program P2C register for given resource node\r
- \r
- @param Base Base address of P2C device\r
+ Program PCI Card device register for given resource node.\r
+\r
+ @param Base Base address of PCI Card device to be programmed.\r
@param Node Given resource node.\r
- \r
- @retval EFI_SUCCESS Success\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramP2C (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
\r
case P2C_BAR_0:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
\r
case P2C_MEM_1:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x1c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_0,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
-\r
//\r
// Set non-prefetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfeff;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
} else {\r
-\r
//\r
// Set pre-fetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0100;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
case P2C_MEM_2:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x24,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x28,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_1,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
\r
// Set non-prefetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfdff;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
} else {\r
\r
//\r
// Set pre-fetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0200;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
case P2C_IO_1:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x2c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
+\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x30,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_0_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
\r
case P2C_IO_2:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x34,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x38,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_1_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Create padding resource node.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
**/\r
-EFI_STATUS\r
+VOID\r
ApplyResourcePadding (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
\r
Ptr++;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Get padding resource for PPB.\r
- Light PCI bus driver woundn't support hotplug root device\r
- So no need to pad resource for them.\r
+ Get padding resource for PCI-PCI bridge.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determines\r
+ whether need to pad resource for them.\r
**/\r
VOID\r
GetResourcePaddingPpb (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
GetResourcePaddingForHpb (PciIoDevice);\r
}\r
projects / mirror_edk2.git / blobdiff