IntelFsp2Pkg: Add FSP*_ARCH_UPD.

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / FspApiEntryT.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index e354870a1daa848f750d8312799d3b68fb5bc76b..7934eab6d7ae59dc2c43b405327391d475abc08c 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -1,7 +1,7 @@
 ;; @file\r
 ;  Provide FSP API entry points.\r
 ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;;\r
 \r
@@ -78,6 +78,23 @@ struc LoadMicrocodeParams
     .size:\r
 endstruc\r
 \r
+struc LoadMicrocodeParamsFsp22\r
+    ; FSP_UPD_HEADER {\r
+    .FspUpdHeaderSignature:   resd    2\r
+    .FspUpdHeaderRevision:    resb    1\r
+    .FspUpdHeaderReserved:    resb   23\r
+    ; }\r
+    ; FSPT_ARCH_UPD{\r
+    .FsptArchUpd:             resd    8\r
+    ; }\r
+    ; FSPT_CORE_UPD {\r
+    .MicrocodeCodeAddr:       resd    1\r
+    .MicrocodeCodeSize:       resd    1\r
+    .CodeRegionBase:          resd    1\r
+    .CodeRegionSize:          resd    1\r
+    ; }\r
+    .size:\r
+endstruc\r
 \r
 ;\r
 ; Define SSE macros\r
@@ -169,6 +186,11 @@ ASM_PFX(LoadMicrocodeDefault):
 \r
    ; skip loading Microcode if the MicrocodeCodeSize is zero\r
    ; and report error if size is less than 2k\r
+   ; first check UPD header revision\r
+   cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+   jae    Fsp22UpdHeader\r
+\r
+   ; UPD structure is compliant with FSP spec 2.0/2.1\r
    mov    eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
    cmp    eax, 0\r
    jz     Exit2\r
@@ -178,6 +200,19 @@ ASM_PFX(LoadMicrocodeDefault):
    mov    esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
    cmp    esi, 0\r
    jnz    CheckMainHeader\r
+   jmp    ParamError\r
+\r
+Fsp22UpdHeader:\r
+   ; UPD structure is compliant with FSP spec 2.2\r
+   mov    eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
+   cmp    eax, 0\r
+   jz     Exit2\r
+   cmp    eax, 0800h\r
+   jl     ParamError\r
+\r
+   mov    esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
+   cmp    esi, 0\r
+   jnz    CheckMainHeader\r
 \r
 ParamError:\r
    mov    eax, 080000002h\r
@@ -276,6 +311,11 @@ CheckAddress:
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
    jz    Done\r
 \r
+   ; Check UPD header revision\r
+   cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+   jae    Fsp22UpdHeader1\r
+\r
+   ; UPD structure is compliant with FSP spec 2.0/2.1\r
    ; Is automatic size detection ?\r
    mov   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
    cmp   eax, 0ffffffffh\r
@@ -287,6 +327,19 @@ CheckAddress:
    jae   Done        ;Jif address is outside of microcode region\r
    jmp   CheckMainHeader\r
 \r
+Fsp22UpdHeader1:\r
+   ; UPD structure is compliant with FSP spec 2.2\r
+   ; Is automatic size detection ?\r
+   mov   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
+   cmp   eax, 0ffffffffh\r
+   jz    LoadMicrocodeDefault4\r
+\r
+   ; Address >= microcode region address + microcode region size?\r
+   add   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
+   cmp   esi, eax\r
+   jae   Done        ;Jif address is outside of microcode region\r
+   jmp   CheckMainHeader\r
+\r
 LoadMicrocodeDefault4:\r
 LoadCheck:\r
    ; Get the revision of the current microcode update loaded\r
@@ -349,11 +402,26 @@ ASM_PFX(EstablishStackFsp):
 \r
   push      DATA_LEN_OF_MCUD     ; Size of the data region\r
   push      4455434Dh            ; Signature of the  data region 'MCUD'\r
-  push      dword [edx + 2Ch]    ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
-  push      dword [edx + 28h]    ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
-  push      dword [edx + 24h]    ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
-  push      dword [edx + 20h]    ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
 \r
+  ; check UPD structure revision (edx + 8)\r
+  cmp       byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+  jae       Fsp22UpdHeader2\r
+\r
+  ; UPD structure is compliant with FSP spec 2.0/2.1\r
+  push      dword [edx + LoadMicrocodeParams.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
+  push      dword [edx + LoadMicrocodeParams.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
+  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
+  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
+  jmp       ContinueAfterUpdPush\r
+\r
+Fsp22UpdHeader2:\r
+  ; UPD structure is compliant with FSP spec 2.2\r
+  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
+  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
+  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
+  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
+\r
+ContinueAfterUpdPush:\r
   ;\r
   ; Save API entry/exit timestamp into stack\r
   ;\r