;; @file\r
; Provide FSP API entry points.\r
;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
.size:\r
endstruc\r
\r
+struc LoadMicrocodeParamsFsp22\r
+ ; FSP_UPD_HEADER {\r
+ .FspUpdHeaderSignature: resd 2\r
+ .FspUpdHeaderRevision: resb 1\r
+ .FspUpdHeaderReserved: resb 23\r
+ ; }\r
+ ; FSPT_ARCH_UPD{\r
+ .FsptArchUpd: resd 8\r
+ ; }\r
+ ; FSPT_CORE_UPD {\r
+ .MicrocodeCodeAddr: resd 1\r
+ .MicrocodeCodeSize: resd 1\r
+ .CodeRegionBase: resd 1\r
+ .CodeRegionSize: resd 1\r
+ ; }\r
+ .size:\r
+endstruc\r
\r
;\r
; Define SSE macros\r
\r
; skip loading Microcode if the MicrocodeCodeSize is zero\r
; and report error if size is less than 2k\r
+ ; first check UPD header revision\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+ jae Fsp22UpdHeader\r
+\r
+ ; UPD structure is compliant with FSP spec 2.0/2.1\r
mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
cmp eax, 0\r
jz Exit2\r
mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
cmp esi, 0\r
jnz CheckMainHeader\r
+ jmp ParamError\r
+\r
+Fsp22UpdHeader:\r
+ ; UPD structure is compliant with FSP spec 2.2\r
+ mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
+ cmp eax, 0\r
+ jz Exit2\r
+ cmp eax, 0800h\r
+ jl ParamError\r
+\r
+ mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
+ cmp esi, 0\r
+ jnz CheckMainHeader\r
\r
ParamError:\r
mov eax, 080000002h\r
cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
jz Done\r
\r
+ ; Check UPD header revision\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+ jae Fsp22UpdHeader1\r
+\r
+ ; UPD structure is compliant with FSP spec 2.0/2.1\r
; Is automatic size detection ?\r
mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
cmp eax, 0ffffffffh\r
jae Done ;Jif address is outside of microcode region\r
jmp CheckMainHeader\r
\r
+Fsp22UpdHeader1:\r
+ ; UPD structure is compliant with FSP spec 2.2\r
+ ; Is automatic size detection ?\r
+ mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
+ cmp eax, 0ffffffffh\r
+ jz LoadMicrocodeDefault4\r
+\r
+ ; Address >= microcode region address + microcode region size?\r
+ add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
+ cmp esi, eax\r
+ jae Done ;Jif address is outside of microcode region\r
+ jmp CheckMainHeader\r
+\r
LoadMicrocodeDefault4:\r
LoadCheck:\r
; Get the revision of the current microcode update loaded\r
\r
push DATA_LEN_OF_MCUD ; Size of the data region\r
push 4455434Dh ; Signature of the data region 'MCUD'\r
- push dword [edx + 2Ch] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
- push dword [edx + 28h] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
- push dword [edx + 24h] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
- push dword [edx + 20h] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
\r
+ ; check UPD structure revision (edx + 8)\r
+ cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+ jae Fsp22UpdHeader2\r
+\r
+ ; UPD structure is compliant with FSP spec 2.0/2.1\r
+ push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
+ push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
+ push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
+ push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
+ jmp ContinueAfterUpdPush\r
+\r
+Fsp22UpdHeader2:\r
+ ; UPD structure is compliant with FSP spec 2.2\r
+ push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
+ push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
+ push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
+ push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
+\r
+ContinueAfterUpdPush:\r
;\r
; Save API entry/exit timestamp into stack\r
;\r
///\r
UINT64 Signature;\r
///\r
- /// Revision of the Data structure. For FSP v2.0 value is 1.\r
+ /// Revision of the Data structure.\r
+ /// For FSP spec 2.0/2.1 value is 1.\r
+ /// For FSP spec 2.2 value is 2.\r
///\r
UINT8 Revision;\r
UINT8 Reserved[23];\r
} FSP_UPD_HEADER;\r
\r
+///\r
+/// FSPT_ARCH_UPD Configuration.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Revision Revision of the structure is 1 for this version of the specification.\r
+ ///\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ ///\r
+ /// Length Length of the structure in bytes. The current value for this field is 32.\r
+ ///\r
+ UINT32 Length;\r
+ ///\r
+ /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
+ /// occurring during FSP execution.\r
+ ///\r
+ FSP_DEBUG_HANDLER FspDebugHandler;\r
+ UINT8 Reserved1[20];\r
+} FSPT_ARCH_UPD;\r
+\r
///\r
/// FSPM_ARCH_UPD Configuration.\r
///\r
UINT8 Reserved1[4];\r
} FSPM_ARCH_UPD;\r
\r
+typedef struct {\r
+ ///\r
+ /// Revision Revision of the structure is 1 for this version of the specification.\r
+ ///\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ ///\r
+ /// Length Length of the structure in bytes. The current value for this field is 32.\r
+ ///\r
+ UINT32 Length;\r
+ ///\r
+ /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
+ /// occurring during FSP execution.\r
+ ///\r
+ FSP_EVENT_HANDLER FspEventHandler;\r
+ ///\r
+ /// A FSP binary may optionally implement multi-phase silicon initialization,\r
+ /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r
+ /// is non-zero.\r
+ /// To enable multi-phase silicon initialization, the bootloader must set\r
+ /// EnableMultiPhaseSiliconInit to a non-zero value.\r
+ ///\r
+ UINT8 EnableMultiPhaseSiliconInit;\r
+ UINT8 Reserved1[19];\r
+} FSPS_ARCH_UPD;\r
+\r
///\r
/// FSPT_UPD_COMMON Configuration.\r
///\r
FSP_UPD_HEADER FspUpdHeader;\r
} FSPT_UPD_COMMON;\r
\r
+///\r
+/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// FSP_UPD_HEADER Configuration.\r
+ ///\r
+ FSP_UPD_HEADER FspUpdHeader;\r
+\r
+ ///\r
+ /// FSPT_ARCH_UPD Configuration.\r
+ ///\r
+ FSPT_ARCH_UPD FsptArchUpd;\r
+} FSPT_UPD_COMMON_FSP22;\r
+\r
///\r
/// FSPM_UPD_COMMON Configuration.\r
///\r
FSP_UPD_HEADER FspUpdHeader;\r
} FSPS_UPD_COMMON;\r
\r
+///\r
+/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// FSP_UPD_HEADER Configuration.\r
+ ///\r
+ FSP_UPD_HEADER FspUpdHeader;\r
+\r
+ ///\r
+ /// FSPS_ARCH_UPD Configuration.\r
+ ///\r
+ FSPS_ARCH_UPD FspsArchUpd;\r
+} FSPS_UPD_COMMON_FSP22;\r
+\r
///\r
/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r
///\r
UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION\r
UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG\r
UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE']\r
- ExcludedSpecificUpd = 'FSPM_ARCH_UPD'\r
+ ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD']\r
\r
if InputHeaderFile != '':\r
if not os.path.exists(InputHeaderFile):\r
if Match:\r
StartIndex = Index - 1\r
Match = re.match("}\s([_A-Z0-9]+);", Line)\r
- if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd not in Match.group(1)):\r
+ if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in Match.group(1)):\r
EndIndex = Index\r
StructStart.append(StartIndex)\r
StructEnd.append(EndIndex)\r
\r
\r
def Usage():\r
- print ("GenCfgOpt Version 0.54")\r
+ print ("GenCfgOpt Version 0.55")\r
print ("Usage:")\r
print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]")\r
print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]")\r
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