IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.

[mirror_edk2.git] / IntelFsp2Pkg / Include / Guid / FspHeaderFile.h

diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
index 16f43a127312c73c97c3a4f98441988710e92088..3474bac1deeedd05217f9b66b632fb150f7b4b30 100644 (file)
--- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
+++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -1,8 +1,8 @@
 /** @file\r
   Intel FSP Header File definition from Intel Firmware Support Package External\r
-  Architecture Specification v2.0.\r
+  Architecture Specification v2.0 and above.\r
 \r
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -110,6 +110,12 @@ typedef struct {
   /// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
   ///\r
   UINT32  FspSiliconInitEntryOffset;\r
+  ///\r
+  /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
+  ///            This value is only valid if FSP HeaderRevision is >= 5.\r
+  ///            If the value is set to 0x00000000, then this API is not available in this component.\r
+  ///\r
+  UINT32  FspMultiPhaseSiInitEntryOffset;\r
 } FSP_INFO_HEADER;\r
 \r
 ///\r