/** @file\r
Intel FSP Header File definition from Intel Firmware Support Package External\r
- Architecture Specification v2.0.\r
+ Architecture Specification v2.0 and above.\r
\r
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
+#include <Base.h>\r
+\r
#ifndef __FSP_HEADER_FILE_H__\r
#define __FSP_HEADER_FILE_H__\r
\r
-#define FSP_HEADER_REVISION_3 3\r
+#define FSP_HEADER_REVISION_3 3\r
\r
#define FSPE_HEADER_REVISION_1 1\r
#define FSPP_HEADER_REVISION_1 1\r
///\r
/// Fixed FSP header offset in the FSP image\r
///\r
-#define FSP_INFO_HEADER_OFF 0x94\r
+#define FSP_INFO_HEADER_OFF 0x94\r
\r
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r
\r
#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')\r
\r
-#pragma pack(1)\r
+#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0\r
+#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1\r
+#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2\r
+#define FSP_IA32 0\r
+#define FSP_X64 1\r
+\r
+ #pragma pack(1)\r
\r
///\r
/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.\r
///\r
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Length of the FSP Information Header.\r
///\r
- UINT32 HeaderLength;\r
+ UINT32 HeaderLength;\r
///\r
/// Byte 0x08: Reserved.\r
///\r
- UINT8 Reserved1[2];\r
+ UINT8 Reserved1[2];\r
///\r
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r
+ /// For revision v2.4 the value will be 0x24.\r
///\r
- UINT8 SpecVersion;\r
+ UINT8 SpecVersion;\r
///\r
/// Byte 0x0B: Revision of the FSP Information Header.\r
+ /// The Current value for this field is 0x7.\r
///\r
- UINT8 HeaderRevision;\r
+ UINT8 HeaderRevision;\r
///\r
/// Byte 0x0C: Revision of the FSP binary.\r
- ///\r
- UINT32 ImageRevision;\r
+ /// Major.Minor.Revision.Build\r
+ /// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:\r
+ /// 7 : 0 - Build Number\r
+ /// 15 : 8 - Revision\r
+ /// 23 : 16 - Minor Version\r
+ /// 31 : 24 - Major Version\r
+ /// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision\r
+ /// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.\r
+ /// 7 : 0 - Low Byte of Build Number\r
+ /// 15 : 8 - Low Byte of Revision\r
+ /// 23 : 16 - Minor Version\r
+ /// 31 : 24 - Major Version\r
+ ///\r
+ UINT32 ImageRevision;\r
///\r
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.\r
///\r
- CHAR8 ImageId[8];\r
+ CHAR8 ImageId[8];\r
///\r
/// Byte 0x18: Size of the entire FSP binary.\r
///\r
- UINT32 ImageSize;\r
+ UINT32 ImageSize;\r
///\r
/// Byte 0x1C: FSP binary preferred base address.\r
///\r
- UINT32 ImageBase;\r
+ UINT32 ImageBase;\r
///\r
/// Byte 0x20: Attribute for the FSP binary.\r
+ /// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.\r
+ /// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.\r
+ /// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.\r
+ /// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.\r
+ /// Bits 15:4 - Reserved\r
///\r
- UINT16 ImageAttribute;\r
+ UINT16 ImageAttribute;\r
///\r
/// Byte 0x22: Attributes of the FSP Component.\r
- ///\r
- UINT16 ComponentAttribute;\r
+ /// Bit 0 - Build Type\r
+ /// 0 - Debug Build\r
+ /// 1 - Release Build\r
+ /// Bit 1 - Release Type\r
+ /// 0 - Test Release\r
+ /// 1 - Official Release\r
+ /// Bit 11:2 - Reserved\r
+ /// Bits 15:12 - Component Type\r
+ /// 0000 - Reserved\r
+ /// 0001 - FSP-T\r
+ /// 0010 - FSP-M\r
+ /// 0011 - FSP-S\r
+ /// 0100 - FSP-I (FSP SMM)\r
+ /// 0101 to 0111 - Reserved\r
+ /// 1000 - FSP-O\r
+ /// 1001 to 1111 - Reserved\r
+ ///\r
+ UINT16 ComponentAttribute;\r
///\r
/// Byte 0x24: Offset of the FSP configuration region.\r
///\r
- UINT32 CfgRegionOffset;\r
+ UINT32 CfgRegionOffset;\r
///\r
/// Byte 0x28: Size of the FSP configuration region.\r
///\r
- UINT32 CfgRegionSize;\r
+ UINT32 CfgRegionSize;\r
///\r
/// Byte 0x2C: Reserved2.\r
///\r
- UINT32 Reserved2;\r
+ UINT32 Reserved2;\r
///\r
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.\r
///\r
- UINT32 TempRamInitEntryOffset;\r
+ UINT32 TempRamInitEntryOffset;\r
///\r
/// Byte 0x34: Reserved3.\r
///\r
- UINT32 Reserved3;\r
+ UINT32 Reserved3;\r
///\r
/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.\r
///\r
- UINT32 NotifyPhaseEntryOffset;\r
+ UINT32 NotifyPhaseEntryOffset;\r
///\r
/// Byte 0x3C: The offset for the API to initialize the memory.\r
///\r
- UINT32 FspMemoryInitEntryOffset;\r
+ UINT32 FspMemoryInitEntryOffset;\r
///\r
/// Byte 0x40: The offset for the API to tear down temporary RAM.\r
///\r
- UINT32 TempRamExitEntryOffset;\r
+ UINT32 TempRamExitEntryOffset;\r
///\r
/// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
///\r
- UINT32 FspSiliconInitEntryOffset;\r
+ UINT32 FspSiliconInitEntryOffset;\r
+ ///\r
+ /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
+ /// This value is only valid if FSP HeaderRevision is >= 5.\r
+ /// If the value is set to 0x00000000, then this API is not available in this component.\r
+ ///\r
+ UINT32 FspMultiPhaseSiInitEntryOffset;\r
+ ///\r
+ /// Byte 0x4C: Extended revision of the FSP binary.\r
+ /// This value is only valid if FSP HeaderRevision is >= 6.\r
+ /// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.\r
+ /// 7 : 0 - High Byte of Build Number\r
+ /// 15 : 8 - High Byte of Revision\r
+ /// The FSP binary build number can be decoded as follows:\r
+ /// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]\r
+ /// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]\r
+ /// Minor Version = ImageRevision[23:16]\r
+ /// Major Version = ImageRevision[31:24]\r
+ ///\r
+ UINT16 ExtendedImageRevision;\r
+ ///\r
+ /// Byte 0x4E: Reserved4.\r
+ ///\r
+ UINT16 Reserved4;\r
+ ///\r
+ /// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.\r
+ ///\r
+ UINT32 FspMultiPhaseMemInitEntryOffset;\r
+ ///\r
+ /// Byte 0x54: Offset for the API to initialize SMM.\r
+ ///\r
+ UINT32 FspSmmInitEntryOffset;\r
} FSP_INFO_HEADER;\r
\r
///\r
///\r
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// Byte 0x08: FSP producer defined revision of the table.\r
///\r
- UINT8 Revision;\r
+ UINT8 Revision;\r
///\r
/// Byte 0x09: Reserved for future use.\r
///\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
///\r
/// Byte 0x0A: FSP producer identification string\r
///\r
- CHAR8 FspProducerId[6];\r
+ CHAR8 FspProducerId[6];\r
///\r
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r
///\r
- UINT32 FspProducerRevision;\r
+ UINT32 FspProducerRevision;\r
///\r
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r
///\r
- UINT32 FspProducerDataSize;\r
+ UINT32 FspProducerDataSize;\r
///\r
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r
///\r
// A generic table search algorithm for additional tables can be implemented with a\r
// signature search algorithm until a terminator signature 'FSPP' is found.\r
//\r
-#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r
+#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE\r
\r
///\r
///\r
/// Byte 0x00: FSP Patch Table Signature "FSPP".\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Size including the PatchData.\r
///\r
- UINT16 HeaderLength;\r
+ UINT16 HeaderLength;\r
///\r
/// Byte 0x06: Revision is set to 0x01.\r
///\r
- UINT8 HeaderRevision;\r
+ UINT8 HeaderRevision;\r
///\r
/// Byte 0x07: Reserved for future use.\r
///\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
///\r
/// Byte 0x08: Number of entries to Patch.\r
///\r
- UINT32 PatchEntryNum;\r
+ UINT32 PatchEntryNum;\r
///\r
/// Byte 0x0C: Patch Data.\r
///\r
-//UINT32 PatchData[];\r
+ // UINT32 PatchData[];\r
} FSP_PATCH_TABLE;\r
\r
-#pragma pack()\r
+ #pragma pack()\r
\r
-extern EFI_GUID gFspHeaderFileGuid;\r
+extern EFI_GUID gFspHeaderFileGuid;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff