BaseTools/BinToPcd: Fix Python 2.7.x compatibility issue

[mirror_edk2.git] / IntelFspPkg / IntelFspPkg.dec

diff --git a/IntelFspPkg/IntelFspPkg.dec b/IntelFspPkg/IntelFspPkg.dec
index 092b3fed01df2a4ab9482e0d3328ed3b61eb6eb0..6f8a6306ab4d415638bb85afa10e0b67bab88507 100644 (file)
--- a/IntelFspPkg/IntelFspPkg.dec
+++ b/IntelFspPkg/IntelFspPkg.dec
@@ -21,6 +21,28 @@
 [Includes]\r
   Include\r
   Include/Private\r
+  \r
+[LibraryClasses]\r
+  ##  @libraryclass  Provides cache-as-ram support.\r
+  CacheAsRamLib|Include/Library/CacheAsRamLib.h\r
+\r
+  ##  @libraryclass  Provides cache setting on MTRR.\r
+  CacheLib|Include/Library/CacheLib.h\r
+\r
+  ##  @libraryclass  Provides debug device abstraction.\r
+  DebugDeviceLib|Include/Library/DebugDeviceLib.h\r
+\r
+  ##  @libraryclass  Provides FSP related services.\r
+  FspCommonLib|Include/Library/FspCommonLib.h\r
+\r
+  ##  @libraryclass  Provides FSP platform related actions.\r
+  FspPlatformLib|Include/Library/FspPlatformLib.h\r
+\r
+  ##  @libraryclass  Provides FSP switch stack function.\r
+  FspSwitchStackLib|Include/Library/FspSwitchStackLib.h\r
+  \r
+  ##  @libraryclass  Provides FSP platform sec related actions.\r
+  FspSecPlatformLib|Include/Library/FspSecPlatformLib.h\r
 \r
 [Guids]\r
   #\r
@@ -33,6 +55,7 @@
   gFspBootLoaderTemporaryMemoryGuid     = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
   gFspReservedMemoryResourceHobGuid     = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
   gFspNonVolatileStorageHobGuid         = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
+  gFspBootLoaderTolumHobGuid            = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1\r
 \r
   # Guid defined by platform\r
   gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }\r
@@ -40,12 +63,15 @@
   gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }\r
 \r
 [PcdsFixedAtBuild]\r
-  gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00108|UINT32|0x00000001\r
-  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase        |0xFEF00000|UINT32|0x10001001\r
-  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize        |    0x2000|UINT32|0x10001002\r
-  gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize     |    0x1000|UINT32|0x10001003\r
-  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry         |        32|UINT32|0x00002001\r
-  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry        |         5|UINT32|0x00002002\r
+  gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001\r
+  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001\r
+  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize         |    0x2000|UINT32|0x10001002\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize      |    0x1000|UINT32|0x10001003\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry          |        32|UINT32|0x00002001\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry         |         6|UINT32|0x00002002\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress       |0xFFF80000|UINT32|0x10000001\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize              |0x00040000|UINT32|0x10000002\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
 \r
 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
   gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r