IntelSiliconPkg/dec: Add VTd policy PCD

[mirror_edk2.git] / IntelSiliconPkg / Include / IndustryStandard / IgdOpRegion.h

diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index c66a45261a4801e94de76bb8a8e0886963d22d94..5ce80a5be841fe29b02adf11babeacd7c8ccaef7 100644 (file)
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -4,6 +4,8 @@
 \r
   https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r
 \r
+  @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)\r
+\r
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -29,7 +31,7 @@
   Sub-structures define the different parts of the OpRegion followed by the\r
   main structure representing the entire OpRegion.\r
 \r
-  @note: These structures are packed to 1 byte offsets because the exact\r
+  @note These structures are packed to 1 byte offsets because the exact\r
   data location is required by the supporting design specification due to\r
   the fact that the data is used by ASL and Graphics driver code compiled\r
   separately.\r
@@ -116,7 +118,7 @@ typedef struct {
   UINT64 FDSS;          ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r
   UINT32 FDSP;          ///< Offset 0x3B2 Size of DSS buffer\r
   UINT32 STAT;          ///< Offset 0x3B6 State Indicator\r
-  UINT8  RM31[0x45];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero\r
+  UINT8  RM31[0x46];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero. Bug in spec 0x45(69)\r
 } IGD_OPREGION_MBOX3;\r
 \r
 ///\r