MdeModulePkg/NvmExpressDxe: Fix MS toolchain /Od 32bit build failure

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
index 406cef4f8ed22f08ee0457bf11417f7dc0c6e3eb..f893251fbc936c77454a4d98af535fdf0047e52d 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
   NVM Express specification.\r
 \r
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -27,6 +27,7 @@
 #define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear\r
 #define NVME_CC_OFFSET           0x0014  // Controller Configuration\r
 #define NVME_CSTS_OFFSET         0x001c  // Controller Status\r
+#define NVME_NSSR_OFFSET         0x0020  // NVM Subsystem Reset\r
 #define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes\r
 #define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address\r
 #define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address\r
@@ -53,8 +54,8 @@ typedef struct {
   UINT8  Rsvd1:5;\r
   UINT8  To;        // Timeout\r
   UINT16 Dstrd:4;\r
-  UINT16 Rsvd2:1;\r
-  UINT16 Css:4;     // Command Sets Supported\r
+  UINT16 Nssrs:1;   // NVM Subsystem Reset Supported NSSRS\r
+  UINT16 Css:4;     // Command Sets Supported - Bit 37\r
   UINT16 Rsvd3:7;\r
   UINT8  Mpsmin:4;\r
   UINT8  Mpsmax:4;\r
@@ -75,7 +76,7 @@ typedef struct {
 typedef struct {\r
   UINT16 En:1;       // Enable\r
   UINT16 Rsvd1:3;\r
-  UINT16 Css:3;      // Command Set Selected\r
+  UINT16 Css:3;      // I/O Command Set Selected\r
   UINT16 Mps:4;      // Memory Page Size\r
   UINT16 Ams:3;      // Arbitration Mechanism Selected\r
   UINT16 Shn:2;      // Shutdown Notification\r
@@ -108,18 +109,11 @@ typedef struct {
 //\r
 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
 //\r
-typedef struct {\r
-  UINT64 Rsvd1:12;\r
-  UINT64 Asqb:52;    // Admin Submission Queue Base Address\r
-} NVME_ASQ;\r
-\r
+#define NVME_ASQ      UINT64\r
 //\r
 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
 //\r
-typedef struct {\r
-  UINT64 Rsvd1:12;\r
-  UINT64 Acqb:52;    // Admin Completion Queue Base Address\r
-} NVME_ACQ;\r
+#define NVME_ACQ      UINT64\r
 \r
 //\r
 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
@@ -333,12 +327,12 @@ typedef struct {
   //\r
   UINT16 Vid;                 /* PCI Vendor ID */\r
   UINT16 Ssvid;               /* PCI sub-system vendor ID */\r
-  UINT8  Sn[20];              /* Produce serial number */\r
+  UINT8  Sn[20];              /* Product serial number */\r
 \r
   UINT8  Mn[40];              /* Proeduct model number */\r
   UINT8  Fr[8];               /* Firmware Revision */\r
   UINT8  Rab;                 /* Recommended Arbitration Burst */\r
-  UINT8  Ieee_oiu[3];         /* Organization Unique Identifier */\r
+  UINT8  Ieee_oui[3];         /* Organization Unique Identifier */\r
   UINT8  Cmic;                /* Multi-interface Capabilities */\r
   UINT8  Mdts;                /* Maximum Data Transfer Size */\r
   UINT8  Cntlid[2];           /* Controller ID */\r
@@ -347,6 +341,10 @@ typedef struct {
   // Admin Command Set Attributes\r
   //\r
   UINT16 Oacs;                /* Optional Admin Command Support */\r
+    #define NAMESPACE_MANAGEMENT_SUPPORTED  BIT3\r
+    #define FW_DOWNLOAD_ACTIVATE_SUPPORTED  BIT2\r
+    #define FORMAT_NVM_SUPPORTED            BIT1\r
+    #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
   UINT8  Acl;                 /* Abort Command Limit */\r
   UINT8  Aerl;                /* Async Event Request Limit */\r
   UINT8  Frmw;                /* Firmware updates */\r
@@ -454,7 +452,7 @@ typedef struct {
   UINT32 Pc:1;                /* Physically Contiguous */\r
   UINT32 Ien:1;               /* Interrupts Enabled */\r
   UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */\r
-  UINT32 Iv:16;               /* Interrupt Vector */\r
+  UINT32 Iv:16;               /* Interrupt Vector for MSI-X or MSI*/\r
 } NVME_ADMIN_CRIOCQ;\r
 \r
 //\r
@@ -555,9 +553,9 @@ typedef struct {
   // CDW 10\r
   //\r
   UINT32 Lid:8;               /* Log Page Identifier */\r
-    #define LID_ERROR_INFO\r
-    #define LID_SMART_INFO\r
-    #define LID_FW_SLOT_INFO\r
+    #define LID_ERROR_INFO   0x1\r
+    #define LID_SMART_INFO   0x2\r
+    #define LID_FW_SLOT_INFO 0x3\r
   UINT32 Rsvd1:8;\r
   UINT32 Numd:12;             /* Number of Dwords */\r
   UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */\r
@@ -717,15 +715,29 @@ typedef struct {
   UINT16 Sct:3;             // Status Code Type\r
   UINT16 Rsvd2:2;\r
   UINT16 Mo:1;              // More\r
-  UINT16 Dnr:1;             // Retry\r
+  UINT16 Dnr:1;             // Do Not Retry\r
 } NVME_CQ;\r
 \r
 //\r
 // Nvm Express Admin cmd opcodes\r
 //\r
-#define NVME_ADMIN_CRIOSQ_OPC                1\r
-#define NVME_ADMIN_CRIOCQ_OPC                5\r
-#define NVME_ADMIN_IDENTIFY_OPC              6\r
+#define NVME_ADMIN_DEIOSQ_CMD                0x00\r
+#define NVME_ADMIN_CRIOSQ_CMD                0x01\r
+#define NVME_ADMIN_GET_LOG_PAGE_CMD          0x02\r
+#define NVME_ADMIN_DEIOCQ_CMD                0x04\r
+#define NVME_ADMIN_CRIOCQ_CMD                0x05\r
+#define NVME_ADMIN_IDENTIFY_CMD              0x06\r
+#define NVME_ADMIN_ABORT_CMD                 0x08\r
+#define NVME_ADMIN_SET_FEATURES_CMD          0x09\r
+#define NVME_ADMIN_GET_FEATURES_CMD          0x0A\r
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD   0x0C\r
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD   0x0D\r
+#define NVME_ADMIN_FW_COMMIT_CMD             0x10\r
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD     0x11\r
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD   0x15\r
+#define NVME_ADMIN_FORMAT_NVM_CMD            0x80\r
+#define NVME_ADMIN_SECURITY_SEND_CMD         0x81\r
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD      0x82\r
 \r
 #define NVME_IO_FLUSH_OPC                    0\r
 #define NVME_IO_WRITE_OPC                    1\r