NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
NVM Express specification.\r
\r
- Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
CommandPacket.QueueType = NVME_IO_QUEUE;\r
\r
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;\r
- CommandPacket.NvmeCmd->Cdw11 = (UINT32)(Lba >> 32);\r
+ CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);\r
CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;\r
\r
CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;\r
CommandPacket.QueueType = NVME_IO_QUEUE;\r
\r
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;\r
- CommandPacket.NvmeCmd->Cdw11 = (UINT32)(Lba >> 32);\r
+ CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);\r
CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;\r
\r
CommandPacket.MetadataBuffer = NULL;\r
NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
NVM Express specification.\r
\r
- Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return Status;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "Asq.Asqb: %lx\n", Asq->Asqb));\r
+ DEBUG ((EFI_D_INFO, "Asq: %lx\n", *Asq));\r
\r
return EFI_SUCCESS;\r
}\r
return Status;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "Acq.Acqb: %lxh\n", Acq->Acqb));\r
+ DEBUG ((EFI_D_INFO, "Acq: %lxh\n", *Acq));\r
\r
return EFI_SUCCESS;\r
}\r
//\r
// Address of admin submission queue.\r
//\r
- Asq.Rsvd1 = 0;\r
- Asq.Asqb = (UINT64)(UINTN)(Private->BufferPciAddr) >> 12;\r
+ Asq = (UINT64)(UINTN)(Private->BufferPciAddr) & ~0xFFF;\r
\r
//\r
// Address of admin completion queue.\r
//\r
- Acq.Rsvd1 = 0;\r
- Acq.Acqb = (UINT64)(UINTN)(Private->BufferPciAddr + EFI_PAGE_SIZE) >> 12;\r
+ Acq = (UINT64)(UINTN)(Private->BufferPciAddr + EFI_PAGE_SIZE) & ~0xFFF;\r
\r
//\r
// Address of I/O submission & completion queue.\r
//\r
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
//\r
-typedef struct {\r
- UINT64 Rsvd1:12;\r
- UINT64 Asqb:52; // Admin Submission Queue Base Address\r
-} NVME_ASQ;\r
-\r
+#define NVME_ASQ UINT64\r
//\r
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
//\r
-typedef struct {\r
- UINT64 Rsvd1:12;\r
- UINT64 Acqb:52; // Admin Completion Queue Base Address\r
-} NVME_ACQ;\r
+#define NVME_ACQ UINT64\r
\r
//\r
// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r