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MdeModulePkg/NvmExpressDxe: Fix MS toolchain /Od 32bit build failure
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
754b489b 5 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
eb290d02
FT		 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _NVME_HCI_H_\r
17#define _NVME_HCI_H_\r
18\r
19#define NVME_BAR 0\r
20\r
21//\r
22// controller register offsets\r
23//\r
24#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
25#define NVME_VER_OFFSET 0x0008 // Version\r
26#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
27#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
28#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
29#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
4ab4497c 30#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
eb290d02
FT		 31#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
32#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
33#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
34#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
35#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
36\r
37//\r
38// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
39// Get the doorbell stride bit shift value from the controller capabilities.\r
40//\r
41#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
42#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
43\r
44\r
45#pragma pack(1)\r
46\r
47//\r
48// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
49//\r
50typedef struct {\r
51 UINT16 Mqes; // Maximum Queue Entries Supported\r
52 UINT8 Cqr:1; // Contiguous Queues Required\r
53 UINT8 Ams:2; // Arbitration Mechanism Supported\r
54 UINT8 Rsvd1:5;\r
55 UINT8 To; // Timeout\r
56 UINT16 Dstrd:4;\r
4ab4497c
TF		 57 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS\r
58 UINT16 Css:4; // Command Sets Supported - Bit 37\r
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FT		 59 UINT16 Rsvd3:7;\r
60 UINT8 Mpsmin:4;\r
61 UINT8 Mpsmax:4;\r
62 UINT8 Rsvd4;\r
63} NVME_CAP;\r
64\r
65//\r
66// 3.1.2 Offset 08h: VS - Version\r
67//\r
68typedef struct {\r
69 UINT16 Mnr; // Minor version number\r
70 UINT16 Mjr; // Major version number\r
71} NVME_VER;\r
72\r
73//\r
74// 3.1.5 Offset 14h: CC - Controller Configuration\r
75//\r
76typedef struct {\r
77 UINT16 En:1; // Enable\r
78 UINT16 Rsvd1:3;\r
4ab4497c 79 UINT16 Css:3; // I/O Command Set Selected\r
eb290d02
FT		 80 UINT16 Mps:4; // Memory Page Size\r
81 UINT16 Ams:3; // Arbitration Mechanism Selected\r
82 UINT16 Shn:2; // Shutdown Notification\r
83 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
84 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
85 UINT8 Rsvd2;\r
86} NVME_CC;\r
87\r
88//\r
89// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
90//\r
91typedef struct {\r
92 UINT32 Rdy:1; // Ready\r
93 UINT32 Cfs:1; // Controller Fatal Status\r
94 UINT32 Shst:2; // Shutdown Status\r
95 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
96 UINT32 Rsvd1:27;\r
97} NVME_CSTS;\r
98\r
99//\r
100// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
101//\r
102typedef struct {\r
103 UINT16 Asqs:12; // Submission Queue Size\r
104 UINT16 Rsvd1:4;\r
105 UINT16 Acqs:12; // Completion Queue Size\r
106 UINT16 Rsvd2:4;\r
107} NVME_AQA;\r
108\r
109//\r
110// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
111//\r
c5921812 112#define NVME_ASQ UINT64\r
eb290d02
FT		 113//\r
114// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
115//\r
c5921812 116#define NVME_ACQ UINT64\r
eb290d02
FT		 117\r
118//\r
119// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
120//\r
121typedef struct {\r
122 UINT16 Sqt;\r
123 UINT16 Rsvd1;\r
124} NVME_SQTDBL;\r
125\r
126//\r
127// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
128//\r
129typedef struct {\r
130 UINT16 Cqh;\r
131 UINT16 Rsvd1;\r
132} NVME_CQHDBL;\r
133\r
134//\r
135// NVM command set structures\r
136//\r
137// Read Command\r
138//\r
139typedef struct {\r
140 //\r
141 // CDW 10, 11\r
142 //\r
143 UINT64 Slba; /* Starting Sector Address */\r
144 //\r
145 // CDW 12\r
146 //\r
147 UINT16 Nlb; /* Number of Sectors */\r
148 UINT16 Rsvd1:10;\r
149 UINT16 Prinfo:4; /* Protection Info Check */\r
150 UINT16 Fua:1; /* Force Unit Access */\r
151 UINT16 Lr:1; /* Limited Retry */\r
152 //\r
153 // CDW 13\r
154 //\r
155 UINT32 Af:4; /* Access Frequency */\r
156 UINT32 Al:2; /* Access Latency */\r
157 UINT32 Sr:1; /* Sequential Request */\r
158 UINT32 In:1; /* Incompressible */\r
159 UINT32 Rsvd2:24;\r
160 //\r
161 // CDW 14\r
162 //\r
163 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
164 //\r
165 // CDW 15\r
166 //\r
167 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
168 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
169} NVME_READ;\r
170\r
171//\r
172// Write Command\r
173//\r
174typedef struct {\r
175 //\r
176 // CDW 10, 11\r
177 //\r
178 UINT64 Slba; /* Starting Sector Address */\r
179 //\r
180 // CDW 12\r
181 //\r
182 UINT16 Nlb; /* Number of Sectors */\r
183 UINT16 Rsvd1:10;\r
184 UINT16 Prinfo:4; /* Protection Info Check */\r
185 UINT16 Fua:1; /* Force Unit Access */\r
186 UINT16 Lr:1; /* Limited Retry */\r
187 //\r
188 // CDW 13\r
189 //\r
190 UINT32 Af:4; /* Access Frequency */\r
191 UINT32 Al:2; /* Access Latency */\r
192 UINT32 Sr:1; /* Sequential Request */\r
193 UINT32 In:1; /* Incompressible */\r
194 UINT32 Rsvd2:24;\r
195 //\r
196 // CDW 14\r
197 //\r
198 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
199 //\r
200 // CDW 15\r
201 //\r
202 UINT16 Lbat; /* Logical Block Application Tag */\r
203 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
204} NVME_WRITE;\r
205\r
206//\r
207// Flush\r
208//\r
209typedef struct {\r
210 //\r
211 // CDW 10\r
212 //\r
213 UINT32 Flush; /* Flush */\r
214} NVME_FLUSH;\r
215\r
216//\r
217// Write Uncorrectable command\r
218//\r
219typedef struct {\r
220 //\r
221 // CDW 10, 11\r
222 //\r
223 UINT64 Slba; /* Starting LBA */\r
224 //\r
225 // CDW 12\r
226 //\r
227 UINT32 Nlb:16; /* Number of Logical Blocks */\r
228 UINT32 Rsvd1:16;\r
229} NVME_WRITE_UNCORRECTABLE;\r
230\r
231//\r
232// Write Zeroes command\r
233//\r
234typedef struct {\r
235 //\r
236 // CDW 10, 11\r
237 //\r
238 UINT64 Slba; /* Starting LBA */\r
239 //\r
240 // CDW 12\r
241 //\r
242 UINT16 Nlb; /* Number of Logical Blocks */\r
243 UINT16 Rsvd1:10;\r
244 UINT16 Prinfo:4; /* Protection Info Check */\r
245 UINT16 Fua:1; /* Force Unit Access */\r
246 UINT16 Lr:1; /* Limited Retry */\r
247 //\r
248 // CDW 13\r
249 //\r
250 UINT32 Rsvd2;\r
251 //\r
252 // CDW 14\r
253 //\r
254 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
255 //\r
256 // CDW 15\r
257 //\r
258 UINT16 Lbat; /* Logical Block Application Tag */\r
259 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
260} NVME_WRITE_ZEROES;\r
261\r
262//\r
263// Compare command\r
264//\r
265typedef struct {\r
266 //\r
267 // CDW 10, 11\r
268 //\r
269 UINT64 Slba; /* Starting LBA */\r
270 //\r
271 // CDW 12\r
272 //\r
273 UINT16 Nlb; /* Number of Logical Blocks */\r
274 UINT16 Rsvd1:10;\r
275 UINT16 Prinfo:4; /* Protection Info Check */\r
276 UINT16 Fua:1; /* Force Unit Access */\r
277 UINT16 Lr:1; /* Limited Retry */\r
278 //\r
279 // CDW 13\r
280 //\r
281 UINT32 Rsvd2;\r
282 //\r
283 // CDW 14\r
284 //\r
285 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
286 //\r
287 // CDW 15\r
288 //\r
289 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
290 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
291} NVME_COMPARE;\r
292\r
293typedef union {\r
294 NVME_READ Read;\r
295 NVME_WRITE Write;\r
296 NVME_FLUSH Flush;\r
297 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
298 NVME_WRITE_ZEROES WriteZeros;\r
299 NVME_COMPARE Compare;\r
300} NVME_CMD;\r
301\r
302typedef struct {\r
303 UINT16 Mp; /* Maximum Power */\r
304 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
305 UINT8 Mps:1; /* Max Power Scale */\r
306 UINT8 Nops:1; /* Non-Operational State */\r
307 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
308 UINT32 Enlat; /* Entry Latency */\r
309 UINT32 Exlat; /* Exit Latency */\r
310 UINT8 Rrt:5; /* Relative Read Throughput */\r
311 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
312 UINT8 Rrl:5; /* Relative Read Leatency */\r
313 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
314 UINT8 Rwt:5; /* Relative Write Throughput */\r
315 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
316 UINT8 Rwl:5; /* Relative Write Leatency */\r
317 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
318 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
319} NVME_PSDESCRIPTOR;\r
320\r
321//\r
322// Identify Controller Data\r
323//\r
324typedef struct {\r
325 //\r
326 // Controller Capabilities and Features 0-255\r
327 //\r
328 UINT16 Vid; /* PCI Vendor ID */\r
329 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
4ab4497c 330 UINT8 Sn[20]; /* Product serial number */\r
eb290d02
FT		 331\r
332 UINT8 Mn[40]; /* Proeduct model number */\r
333 UINT8 Fr[8]; /* Firmware Revision */\r
334 UINT8 Rab; /* Recommended Arbitration Burst */\r
4ab4497c 335 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
eb290d02
FT		 336 UINT8 Cmic; /* Multi-interface Capabilities */\r
337 UINT8 Mdts; /* Maximum Data Transfer Size */\r
338 UINT8 Cntlid[2]; /* Controller ID */\r
339 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
340 //\r
341 // Admin Command Set Attributes\r
342 //\r
343 UINT16 Oacs; /* Optional Admin Command Support */\r
754b489b
TF		 344 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3\r
345 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2\r
346 #define FORMAT_NVM_SUPPORTED BIT1\r
347 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
eb290d02
FT		 348 UINT8 Acl; /* Abort Command Limit */\r
349 UINT8 Aerl; /* Async Event Request Limit */\r
350 UINT8 Frmw; /* Firmware updates */\r
351 UINT8 Lpa; /* Log Page Attributes */\r
352 UINT8 Elpe; /* Error Log Page Entries */\r
353 UINT8 Npss; /* Number of Power States Support */\r
354 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
355 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
356 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
357 //\r
358 // NVM Command Set Attributes\r
359 //\r
360 UINT8 Sqes; /* Submission Queue Entry Size */\r
361 UINT8 Cqes; /* Completion Queue Entry Size */\r
362 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
363 UINT32 Nn; /* Number of Namespaces */\r
364 UINT16 Oncs; /* Optional NVM Command Support */\r
365 UINT16 Fuses; /* Fused Operation Support */\r
366 UINT8 Fna; /* Format NVM Attributes */\r
367 UINT8 Vwc; /* Volatile Write Cache */\r
368 UINT16 Awun; /* Atomic Write Unit Normal */\r
369 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
370 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
371 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
372 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
373 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
374 UINT32 Sgls; /* SGL Support */\r
375 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
376 //\r
377 // I/O Command set Attributes\r
378 //\r
379 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
380 //\r
381 // Power State Descriptors\r
382 //\r
383 NVME_PSDESCRIPTOR PsDescriptor[32];\r
384\r
385 UINT8 VendorData[1024]; /* Vendor specific data */\r
386} NVME_ADMIN_CONTROLLER_DATA;\r
387\r
388typedef struct {\r
389 UINT16 Ms; /* Metadata Size */\r
390 UINT8 Lbads; /* LBA Data Size */\r
391 UINT8 Rp:2; /* Relative Performance */\r
392 #define LBAF_RP_BEST 00b\r
393 #define LBAF_RP_BETTER 01b\r
394 #define LBAF_RP_GOOD 10b\r
395 #define LBAF_RP_DEGRADED 11b\r
396 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
397} NVME_LBAFORMAT;\r
398\r
399//\r
400// Identify Namespace Data\r
401//\r
402typedef struct {\r
403 //\r
404 // NVM Command Set Specific\r
405 //\r
406 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
407 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
408 UINT64 Nuse; /* Namespace Utilization */\r
409 UINT8 Nsfeat; /* Namespace Features */\r
410 UINT8 Nlbaf; /* Number of LBA Formats */\r
411 UINT8 Flbas; /* Formatted LBA size */\r
412 UINT8 Mc; /* Metadata Capabilities */\r
413 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
414 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
415 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
416 UINT8 Rescap; /* Reservation Capabilities */\r
417 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
418 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
419 //\r
420 // LBA Format\r
421 //\r
422 NVME_LBAFORMAT LbaFormat[16];\r
423\r
424 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
425 UINT8 VendorData[3712]; /* Vendor specific data */\r
426} NVME_ADMIN_NAMESPACE_DATA;\r
427\r
428//\r
429// NvmExpress Admin Identify Cmd\r
430//\r
431typedef struct {\r
432 //\r
433 // CDW 10\r
434 //\r
435 UINT32 Cns:2;\r
436 UINT32 Rsvd1:30;\r
437} NVME_ADMIN_IDENTIFY;\r
438\r
439//\r
440// NvmExpress Admin Create I/O Completion Queue\r
441//\r
442typedef struct {\r
443 //\r
444 // CDW 10\r
445 //\r
446 UINT32 Qid:16; /* Queue Identifier */\r
447 UINT32 Qsize:16; /* Queue Size */\r
448\r
449 //\r
450 // CDW 11\r
451 //\r
452 UINT32 Pc:1; /* Physically Contiguous */\r
453 UINT32 Ien:1; /* Interrupts Enabled */\r
454 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
4ab4497c 455 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/\r
eb290d02
FT		 456} NVME_ADMIN_CRIOCQ;\r
457\r
458//\r
459// NvmExpress Admin Create I/O Submission Queue\r
460//\r
461typedef struct {\r
462 //\r
463 // CDW 10\r
464 //\r
465 UINT32 Qid:16; /* Queue Identifier */\r
466 UINT32 Qsize:16; /* Queue Size */\r
467\r
468 //\r
469 // CDW 11\r
470 //\r
471 UINT32 Pc:1; /* Physically Contiguous */\r
472 UINT32 Qprio:2; /* Queue Priority */\r
473 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
474 UINT32 Cqid:16; /* Completion Queue ID */\r
475} NVME_ADMIN_CRIOSQ;\r
476\r
477//\r
478// NvmExpress Admin Delete I/O Completion Queue\r
479//\r
480typedef struct {\r
481 //\r
482 // CDW 10\r
483 //\r
484 UINT16 Qid;\r
485 UINT16 Rsvd1;\r
486} NVME_ADMIN_DEIOCQ;\r
487\r
488//\r
489// NvmExpress Admin Delete I/O Submission Queue\r
490//\r
491typedef struct {\r
492 //\r
493 // CDW 10\r
494 //\r
495 UINT16 Qid;\r
496 UINT16 Rsvd1;\r
497} NVME_ADMIN_DEIOSQ;\r
498\r
499//\r
500// NvmExpress Admin Abort Command\r
501//\r
502typedef struct {\r
503 //\r
504 // CDW 10\r
505 //\r
506 UINT32 Sqid:16; /* Submission Queue identifier */\r
507 UINT32 Cid:16; /* Command Identifier */\r
508} NVME_ADMIN_ABORT;\r
509\r
510//\r
511// NvmExpress Admin Firmware Activate Command\r
512//\r
513typedef struct {\r
514 //\r
515 // CDW 10\r
516 //\r
517 UINT32 Fs:3; /* Submission Queue identifier */\r
518 UINT32 Aa:2; /* Command Identifier */\r
519 UINT32 Rsvd1:27;\r
520} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
521\r
522//\r
523// NvmExpress Admin Firmware Image Download Command\r
524//\r
525typedef struct {\r
526 //\r
527 // CDW 10\r
528 //\r
529 UINT32 Numd; /* Number of Dwords */\r
530 //\r
531 // CDW 11\r
532 //\r
533 UINT32 Ofst; /* Offset */\r
534} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
535\r
536//\r
537// NvmExpress Admin Get Features Command\r
538//\r
539typedef struct {\r
540 //\r
541 // CDW 10\r
542 //\r
543 UINT32 Fid:8; /* Feature Identifier */\r
544 UINT32 Sel:3; /* Select */\r
545 UINT32 Rsvd1:21;\r
546} NVME_ADMIN_GET_FEATURES;\r
547\r
548//\r
549// NvmExpress Admin Get Log Page Command\r
550//\r
551typedef struct {\r
552 //\r
553 // CDW 10\r
554 //\r
555 UINT32 Lid:8; /* Log Page Identifier */\r
754b489b
TF		 556 #define LID_ERROR_INFO 0x1\r
557 #define LID_SMART_INFO 0x2\r
558 #define LID_FW_SLOT_INFO 0x3\r
eb290d02
FT		 559 UINT32 Rsvd1:8;\r
560 UINT32 Numd:12; /* Number of Dwords */\r
561 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
562} NVME_ADMIN_GET_LOG_PAGE;\r
563\r
564//\r
565// NvmExpress Admin Set Features Command\r
566//\r
567typedef struct {\r
568 //\r
569 // CDW 10\r
570 //\r
571 UINT32 Fid:8; /* Feature Identifier */\r
572 UINT32 Rsvd1:23;\r
573 UINT32 Sv:1; /* Save */\r
574} NVME_ADMIN_SET_FEATURES;\r
575\r
576//\r
577// NvmExpress Admin Format NVM Command\r
578//\r
579typedef struct {\r
580 //\r
581 // CDW 10\r
582 //\r
583 UINT32 Lbaf:4; /* LBA Format */\r
584 UINT32 Ms:1; /* Metadata Settings */\r
585 UINT32 Pi:3; /* Protection Information */\r
586 UINT32 Pil:1; /* Protection Information Location */\r
587 UINT32 Ses:3; /* Secure Erase Settings */\r
588 UINT32 Rsvd1:20;\r
589} NVME_ADMIN_FORMAT_NVM;\r
590\r
591//\r
592// NvmExpress Admin Security Receive Command\r
593//\r
594typedef struct {\r
595 //\r
596 // CDW 10\r
597 //\r
598 UINT32 Rsvd1:8;\r
599 UINT32 Spsp:16; /* SP Specific */\r
600 UINT32 Secp:8; /* Security Protocol */\r
601 //\r
602 // CDW 11\r
603 //\r
604 UINT32 Al; /* Allocation Length */\r
605} NVME_ADMIN_SECURITY_RECEIVE;\r
606\r
607//\r
608// NvmExpress Admin Security Send Command\r
609//\r
610typedef struct {\r
611 //\r
612 // CDW 10\r
613 //\r
614 UINT32 Rsvd1:8;\r
615 UINT32 Spsp:16; /* SP Specific */\r
616 UINT32 Secp:8; /* Security Protocol */\r
617 //\r
618 // CDW 11\r
619 //\r
620 UINT32 Tl; /* Transfer Length */\r
621} NVME_ADMIN_SECURITY_SEND;\r
622\r
623typedef union {\r
624 NVME_ADMIN_IDENTIFY Identify;\r
625 NVME_ADMIN_CRIOCQ CrIoCq;\r
626 NVME_ADMIN_CRIOSQ CrIoSq;\r
627 NVME_ADMIN_DEIOCQ DeIoCq;\r
628 NVME_ADMIN_DEIOSQ DeIoSq;\r
629 NVME_ADMIN_ABORT Abort;\r
630 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
631 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
632 NVME_ADMIN_GET_FEATURES GetFeatures;\r
633 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
634 NVME_ADMIN_SET_FEATURES SetFeatures;\r
635 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
636 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
637 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
638} NVME_ADMIN_CMD;\r
639\r
640typedef struct {\r
641 UINT32 Cdw10;\r
642 UINT32 Cdw11;\r
643 UINT32 Cdw12;\r
644 UINT32 Cdw13;\r
645 UINT32 Cdw14;\r
646 UINT32 Cdw15;\r
647} NVME_RAW;\r
648\r
649typedef union {\r
650 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
651 NVME_CMD Nvm; // Union of Nvm commands\r
652 NVME_RAW Raw;\r
653} NVME_PAYLOAD;\r
654\r
655//\r
656// Submission Queue\r
657//\r
658typedef struct {\r
659 //\r
660 // CDW 0, Common to all comnmands\r
661 //\r
662 UINT8 Opc; // Opcode\r
663 UINT8 Fuse:2; // Fused Operation\r
664 UINT8 Rsvd1:5;\r
665 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
666 UINT16 Cid; // Command Identifier\r
667\r
668 //\r
669 // CDW 1\r
670 //\r
671 UINT32 Nsid; // Namespace Identifier\r
672\r
673 //\r
674 // CDW 2,3\r
675 //\r
676 UINT64 Rsvd2;\r
677\r
678 //\r
679 // CDW 4,5\r
680 //\r
681 UINT64 Mptr; // Metadata Pointer\r
682\r
683 //\r
684 // CDW 6-9\r
685 //\r
686 UINT64 Prp[2]; // First and second PRP entries\r
687\r
688 NVME_PAYLOAD Payload;\r
689\r
690} NVME_SQ;\r
691\r
692//\r
693// Completion Queue\r
694//\r
695typedef struct {\r
696 //\r
697 // CDW 0\r
698 //\r
699 UINT32 Dword0;\r
700 //\r
701 // CDW 1\r
702 //\r
703 UINT32 Rsvd1;\r
704 //\r
705 // CDW 2\r
706 //\r
707 UINT16 Sqhd; // Submission Queue Head Pointer\r
708 UINT16 Sqid; // Submission Queue Identifier\r
709 //\r
710 // CDW 3\r
711 //\r
712 UINT16 Cid; // Command Identifier\r
713 UINT16 Pt:1; // Phase Tag\r
714 UINT16 Sc:8; // Status Code\r
715 UINT16 Sct:3; // Status Code Type\r
716 UINT16 Rsvd2:2;\r
717 UINT16 Mo:1; // More\r
4ab4497c 718 UINT16 Dnr:1; // Do Not Retry\r
eb290d02
FT		 719} NVME_CQ;\r
720\r
721//\r
722// Nvm Express Admin cmd opcodes\r
723//\r
754b489b
TF		 724#define NVME_ADMIN_DEIOSQ_CMD 0x00\r
725#define NVME_ADMIN_CRIOSQ_CMD 0x01\r
726#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02\r
727#define NVME_ADMIN_DEIOCQ_CMD 0x04\r
728#define NVME_ADMIN_CRIOCQ_CMD 0x05\r
729#define NVME_ADMIN_IDENTIFY_CMD 0x06\r
730#define NVME_ADMIN_ABORT_CMD 0x08\r
731#define NVME_ADMIN_SET_FEATURES_CMD 0x09\r
732#define NVME_ADMIN_GET_FEATURES_CMD 0x0A\r
733#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C\r
734#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D\r
735#define NVME_ADMIN_FW_COMMIT_CMD 0x10\r
736#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11\r
737#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15\r
738#define NVME_ADMIN_FORMAT_NVM_CMD 0x80\r
739#define NVME_ADMIN_SECURITY_SEND_CMD 0x81\r
740#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82\r
eb290d02
FT		 741\r
742#define NVME_IO_FLUSH_OPC 0\r
743#define NVME_IO_WRITE_OPC 1\r
744#define NVME_IO_READ_OPC 2\r
745\r
746//\r
747// Offset from the beginning of private data queue buffer\r
748//\r
749#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r
750\r
751/**\r
752 Initialize the Nvm Express controller.\r
753\r
754 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
755\r
756 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r
757 @retval Others A device error occurred while initializing the controller.\r
758\r
759**/\r
760EFI_STATUS\r
761NvmeControllerInit (\r
762 IN NVME_CONTROLLER_PRIVATE_DATA *Private\r
763 );\r
764\r
765/**\r
766 Get identify controller data.\r
767\r
768 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
769 @param Buffer The buffer used to store the identify controller data.\r
770\r
771 @return EFI_SUCCESS Successfully get the identify controller data.\r
772 @return EFI_DEVICE_ERROR Fail to get the identify controller data.\r
773\r
774**/\r
775EFI_STATUS\r
776NvmeIdentifyController (\r
777 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
778 IN VOID *Buffer\r
779 );\r
780\r
781/**\r
782 Get specified identify namespace data.\r
783\r
784 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
785 @param NamespaceId The specified namespace identifier.\r
786 @param Buffer The buffer used to store the identify namespace data.\r
787\r
788 @return EFI_SUCCESS Successfully get the identify namespace data.\r
789 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r
790\r
791**/\r
792EFI_STATUS\r
793NvmeIdentifyNamespace (\r
794 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
795 IN UINT32 NamespaceId,\r
796 IN VOID *Buffer\r
797 );\r
798\r
799#pragma pack()\r
800\r
801#endif\r
802\r
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