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MdeMdeModulePkg/NvmExpressDxe: Add NVM Express support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
5 Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _NVME_HCI_H_\r
17#define _NVME_HCI_H_\r
18\r
19#define NVME_BAR 0\r
20\r
21//\r
22// controller register offsets\r
23//\r
24#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
25#define NVME_VER_OFFSET 0x0008 // Version\r
26#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
27#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
28#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
29#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
30#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
31#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
32#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
33#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
34#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
35\r
36//\r
37// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
38// Get the doorbell stride bit shift value from the controller capabilities.\r
39//\r
40#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
41#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
42\r
43\r
44#pragma pack(1)\r
45\r
46//\r
47// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
48//\r
49typedef struct {\r
50 UINT16 Mqes; // Maximum Queue Entries Supported\r
51 UINT8 Cqr:1; // Contiguous Queues Required\r
52 UINT8 Ams:2; // Arbitration Mechanism Supported\r
53 UINT8 Rsvd1:5;\r
54 UINT8 To; // Timeout\r
55 UINT16 Dstrd:4;\r
56 UINT16 Rsvd2:1;\r
57 UINT16 Css:4; // Command Sets Supported\r
58 UINT16 Rsvd3:7;\r
59 UINT8 Mpsmin:4;\r
60 UINT8 Mpsmax:4;\r
61 UINT8 Rsvd4;\r
62} NVME_CAP;\r
63\r
64//\r
65// 3.1.2 Offset 08h: VS - Version\r
66//\r
67typedef struct {\r
68 UINT16 Mnr; // Minor version number\r
69 UINT16 Mjr; // Major version number\r
70} NVME_VER;\r
71\r
72//\r
73// 3.1.5 Offset 14h: CC - Controller Configuration\r
74//\r
75typedef struct {\r
76 UINT16 En:1; // Enable\r
77 UINT16 Rsvd1:3;\r
78 UINT16 Css:3; // Command Set Selected\r
79 UINT16 Mps:4; // Memory Page Size\r
80 UINT16 Ams:3; // Arbitration Mechanism Selected\r
81 UINT16 Shn:2; // Shutdown Notification\r
82 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
83 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
84 UINT8 Rsvd2;\r
85} NVME_CC;\r
86\r
87//\r
88// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
89//\r
90typedef struct {\r
91 UINT32 Rdy:1; // Ready\r
92 UINT32 Cfs:1; // Controller Fatal Status\r
93 UINT32 Shst:2; // Shutdown Status\r
94 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
95 UINT32 Rsvd1:27;\r
96} NVME_CSTS;\r
97\r
98//\r
99// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
100//\r
101typedef struct {\r
102 UINT16 Asqs:12; // Submission Queue Size\r
103 UINT16 Rsvd1:4;\r
104 UINT16 Acqs:12; // Completion Queue Size\r
105 UINT16 Rsvd2:4;\r
106} NVME_AQA;\r
107\r
108//\r
109// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
110//\r
111typedef struct {\r
112 UINT64 Rsvd1:12;\r
113 UINT64 Asqb:52; // Admin Submission Queue Base Address\r
114} NVME_ASQ;\r
115\r
116//\r
117// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
118//\r
119typedef struct {\r
120 UINT64 Rsvd1:12;\r
121 UINT64 Acqb:52; // Admin Completion Queue Base Address\r
122} NVME_ACQ;\r
123\r
124//\r
125// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
126//\r
127typedef struct {\r
128 UINT16 Sqt;\r
129 UINT16 Rsvd1;\r
130} NVME_SQTDBL;\r
131\r
132//\r
133// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
134//\r
135typedef struct {\r
136 UINT16 Cqh;\r
137 UINT16 Rsvd1;\r
138} NVME_CQHDBL;\r
139\r
140//\r
141// NVM command set structures\r
142//\r
143// Read Command\r
144//\r
145typedef struct {\r
146 //\r
147 // CDW 10, 11\r
148 //\r
149 UINT64 Slba; /* Starting Sector Address */\r
150 //\r
151 // CDW 12\r
152 //\r
153 UINT16 Nlb; /* Number of Sectors */\r
154 UINT16 Rsvd1:10;\r
155 UINT16 Prinfo:4; /* Protection Info Check */\r
156 UINT16 Fua:1; /* Force Unit Access */\r
157 UINT16 Lr:1; /* Limited Retry */\r
158 //\r
159 // CDW 13\r
160 //\r
161 UINT32 Af:4; /* Access Frequency */\r
162 UINT32 Al:2; /* Access Latency */\r
163 UINT32 Sr:1; /* Sequential Request */\r
164 UINT32 In:1; /* Incompressible */\r
165 UINT32 Rsvd2:24;\r
166 //\r
167 // CDW 14\r
168 //\r
169 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
170 //\r
171 // CDW 15\r
172 //\r
173 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
174 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
175} NVME_READ;\r
176\r
177//\r
178// Write Command\r
179//\r
180typedef struct {\r
181 //\r
182 // CDW 10, 11\r
183 //\r
184 UINT64 Slba; /* Starting Sector Address */\r
185 //\r
186 // CDW 12\r
187 //\r
188 UINT16 Nlb; /* Number of Sectors */\r
189 UINT16 Rsvd1:10;\r
190 UINT16 Prinfo:4; /* Protection Info Check */\r
191 UINT16 Fua:1; /* Force Unit Access */\r
192 UINT16 Lr:1; /* Limited Retry */\r
193 //\r
194 // CDW 13\r
195 //\r
196 UINT32 Af:4; /* Access Frequency */\r
197 UINT32 Al:2; /* Access Latency */\r
198 UINT32 Sr:1; /* Sequential Request */\r
199 UINT32 In:1; /* Incompressible */\r
200 UINT32 Rsvd2:24;\r
201 //\r
202 // CDW 14\r
203 //\r
204 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
205 //\r
206 // CDW 15\r
207 //\r
208 UINT16 Lbat; /* Logical Block Application Tag */\r
209 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
210} NVME_WRITE;\r
211\r
212//\r
213// Flush\r
214//\r
215typedef struct {\r
216 //\r
217 // CDW 10\r
218 //\r
219 UINT32 Flush; /* Flush */\r
220} NVME_FLUSH;\r
221\r
222//\r
223// Write Uncorrectable command\r
224//\r
225typedef struct {\r
226 //\r
227 // CDW 10, 11\r
228 //\r
229 UINT64 Slba; /* Starting LBA */\r
230 //\r
231 // CDW 12\r
232 //\r
233 UINT32 Nlb:16; /* Number of Logical Blocks */\r
234 UINT32 Rsvd1:16;\r
235} NVME_WRITE_UNCORRECTABLE;\r
236\r
237//\r
238// Write Zeroes command\r
239//\r
240typedef struct {\r
241 //\r
242 // CDW 10, 11\r
243 //\r
244 UINT64 Slba; /* Starting LBA */\r
245 //\r
246 // CDW 12\r
247 //\r
248 UINT16 Nlb; /* Number of Logical Blocks */\r
249 UINT16 Rsvd1:10;\r
250 UINT16 Prinfo:4; /* Protection Info Check */\r
251 UINT16 Fua:1; /* Force Unit Access */\r
252 UINT16 Lr:1; /* Limited Retry */\r
253 //\r
254 // CDW 13\r
255 //\r
256 UINT32 Rsvd2;\r
257 //\r
258 // CDW 14\r
259 //\r
260 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
261 //\r
262 // CDW 15\r
263 //\r
264 UINT16 Lbat; /* Logical Block Application Tag */\r
265 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
266} NVME_WRITE_ZEROES;\r
267\r
268//\r
269// Compare command\r
270//\r
271typedef struct {\r
272 //\r
273 // CDW 10, 11\r
274 //\r
275 UINT64 Slba; /* Starting LBA */\r
276 //\r
277 // CDW 12\r
278 //\r
279 UINT16 Nlb; /* Number of Logical Blocks */\r
280 UINT16 Rsvd1:10;\r
281 UINT16 Prinfo:4; /* Protection Info Check */\r
282 UINT16 Fua:1; /* Force Unit Access */\r
283 UINT16 Lr:1; /* Limited Retry */\r
284 //\r
285 // CDW 13\r
286 //\r
287 UINT32 Rsvd2;\r
288 //\r
289 // CDW 14\r
290 //\r
291 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
292 //\r
293 // CDW 15\r
294 //\r
295 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
296 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
297} NVME_COMPARE;\r
298\r
299typedef union {\r
300 NVME_READ Read;\r
301 NVME_WRITE Write;\r
302 NVME_FLUSH Flush;\r
303 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
304 NVME_WRITE_ZEROES WriteZeros;\r
305 NVME_COMPARE Compare;\r
306} NVME_CMD;\r
307\r
308typedef struct {\r
309 UINT16 Mp; /* Maximum Power */\r
310 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
311 UINT8 Mps:1; /* Max Power Scale */\r
312 UINT8 Nops:1; /* Non-Operational State */\r
313 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
314 UINT32 Enlat; /* Entry Latency */\r
315 UINT32 Exlat; /* Exit Latency */\r
316 UINT8 Rrt:5; /* Relative Read Throughput */\r
317 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
318 UINT8 Rrl:5; /* Relative Read Leatency */\r
319 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
320 UINT8 Rwt:5; /* Relative Write Throughput */\r
321 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
322 UINT8 Rwl:5; /* Relative Write Leatency */\r
323 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
324 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
325} NVME_PSDESCRIPTOR;\r
326\r
327//\r
328// Identify Controller Data\r
329//\r
330typedef struct {\r
331 //\r
332 // Controller Capabilities and Features 0-255\r
333 //\r
334 UINT16 Vid; /* PCI Vendor ID */\r
335 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
336 UINT8 Sn[20]; /* Produce serial number */\r
337\r
338 UINT8 Mn[40]; /* Proeduct model number */\r
339 UINT8 Fr[8]; /* Firmware Revision */\r
340 UINT8 Rab; /* Recommended Arbitration Burst */\r
341 UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */\r
342 UINT8 Cmic; /* Multi-interface Capabilities */\r
343 UINT8 Mdts; /* Maximum Data Transfer Size */\r
344 UINT8 Cntlid[2]; /* Controller ID */\r
345 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
346 //\r
347 // Admin Command Set Attributes\r
348 //\r
349 UINT16 Oacs; /* Optional Admin Command Support */\r
350 UINT8 Acl; /* Abort Command Limit */\r
351 UINT8 Aerl; /* Async Event Request Limit */\r
352 UINT8 Frmw; /* Firmware updates */\r
353 UINT8 Lpa; /* Log Page Attributes */\r
354 UINT8 Elpe; /* Error Log Page Entries */\r
355 UINT8 Npss; /* Number of Power States Support */\r
356 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
357 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
358 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
359 //\r
360 // NVM Command Set Attributes\r
361 //\r
362 UINT8 Sqes; /* Submission Queue Entry Size */\r
363 UINT8 Cqes; /* Completion Queue Entry Size */\r
364 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
365 UINT32 Nn; /* Number of Namespaces */\r
366 UINT16 Oncs; /* Optional NVM Command Support */\r
367 UINT16 Fuses; /* Fused Operation Support */\r
368 UINT8 Fna; /* Format NVM Attributes */\r
369 UINT8 Vwc; /* Volatile Write Cache */\r
370 UINT16 Awun; /* Atomic Write Unit Normal */\r
371 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
372 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
373 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
374 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
375 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
376 UINT32 Sgls; /* SGL Support */\r
377 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
378 //\r
379 // I/O Command set Attributes\r
380 //\r
381 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
382 //\r
383 // Power State Descriptors\r
384 //\r
385 NVME_PSDESCRIPTOR PsDescriptor[32];\r
386\r
387 UINT8 VendorData[1024]; /* Vendor specific data */\r
388} NVME_ADMIN_CONTROLLER_DATA;\r
389\r
390typedef struct {\r
391 UINT16 Ms; /* Metadata Size */\r
392 UINT8 Lbads; /* LBA Data Size */\r
393 UINT8 Rp:2; /* Relative Performance */\r
394 #define LBAF_RP_BEST 00b\r
395 #define LBAF_RP_BETTER 01b\r
396 #define LBAF_RP_GOOD 10b\r
397 #define LBAF_RP_DEGRADED 11b\r
398 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
399} NVME_LBAFORMAT;\r
400\r
401//\r
402// Identify Namespace Data\r
403//\r
404typedef struct {\r
405 //\r
406 // NVM Command Set Specific\r
407 //\r
408 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
409 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
410 UINT64 Nuse; /* Namespace Utilization */\r
411 UINT8 Nsfeat; /* Namespace Features */\r
412 UINT8 Nlbaf; /* Number of LBA Formats */\r
413 UINT8 Flbas; /* Formatted LBA size */\r
414 UINT8 Mc; /* Metadata Capabilities */\r
415 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
416 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
417 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
418 UINT8 Rescap; /* Reservation Capabilities */\r
419 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
420 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
421 //\r
422 // LBA Format\r
423 //\r
424 NVME_LBAFORMAT LbaFormat[16];\r
425\r
426 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
427 UINT8 VendorData[3712]; /* Vendor specific data */\r
428} NVME_ADMIN_NAMESPACE_DATA;\r
429\r
430//\r
431// NvmExpress Admin Identify Cmd\r
432//\r
433typedef struct {\r
434 //\r
435 // CDW 10\r
436 //\r
437 UINT32 Cns:2;\r
438 UINT32 Rsvd1:30;\r
439} NVME_ADMIN_IDENTIFY;\r
440\r
441//\r
442// NvmExpress Admin Create I/O Completion Queue\r
443//\r
444typedef struct {\r
445 //\r
446 // CDW 10\r
447 //\r
448 UINT32 Qid:16; /* Queue Identifier */\r
449 UINT32 Qsize:16; /* Queue Size */\r
450\r
451 //\r
452 // CDW 11\r
453 //\r
454 UINT32 Pc:1; /* Physically Contiguous */\r
455 UINT32 Ien:1; /* Interrupts Enabled */\r
456 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
457 UINT32 Iv:16; /* Interrupt Vector */\r
458} NVME_ADMIN_CRIOCQ;\r
459\r
460//\r
461// NvmExpress Admin Create I/O Submission Queue\r
462//\r
463typedef struct {\r
464 //\r
465 // CDW 10\r
466 //\r
467 UINT32 Qid:16; /* Queue Identifier */\r
468 UINT32 Qsize:16; /* Queue Size */\r
469\r
470 //\r
471 // CDW 11\r
472 //\r
473 UINT32 Pc:1; /* Physically Contiguous */\r
474 UINT32 Qprio:2; /* Queue Priority */\r
475 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
476 UINT32 Cqid:16; /* Completion Queue ID */\r
477} NVME_ADMIN_CRIOSQ;\r
478\r
479//\r
480// NvmExpress Admin Delete I/O Completion Queue\r
481//\r
482typedef struct {\r
483 //\r
484 // CDW 10\r
485 //\r
486 UINT16 Qid;\r
487 UINT16 Rsvd1;\r
488} NVME_ADMIN_DEIOCQ;\r
489\r
490//\r
491// NvmExpress Admin Delete I/O Submission Queue\r
492//\r
493typedef struct {\r
494 //\r
495 // CDW 10\r
496 //\r
497 UINT16 Qid;\r
498 UINT16 Rsvd1;\r
499} NVME_ADMIN_DEIOSQ;\r
500\r
501//\r
502// NvmExpress Admin Abort Command\r
503//\r
504typedef struct {\r
505 //\r
506 // CDW 10\r
507 //\r
508 UINT32 Sqid:16; /* Submission Queue identifier */\r
509 UINT32 Cid:16; /* Command Identifier */\r
510} NVME_ADMIN_ABORT;\r
511\r
512//\r
513// NvmExpress Admin Firmware Activate Command\r
514//\r
515typedef struct {\r
516 //\r
517 // CDW 10\r
518 //\r
519 UINT32 Fs:3; /* Submission Queue identifier */\r
520 UINT32 Aa:2; /* Command Identifier */\r
521 UINT32 Rsvd1:27;\r
522} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
523\r
524//\r
525// NvmExpress Admin Firmware Image Download Command\r
526//\r
527typedef struct {\r
528 //\r
529 // CDW 10\r
530 //\r
531 UINT32 Numd; /* Number of Dwords */\r
532 //\r
533 // CDW 11\r
534 //\r
535 UINT32 Ofst; /* Offset */\r
536} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
537\r
538//\r
539// NvmExpress Admin Get Features Command\r
540//\r
541typedef struct {\r
542 //\r
543 // CDW 10\r
544 //\r
545 UINT32 Fid:8; /* Feature Identifier */\r
546 UINT32 Sel:3; /* Select */\r
547 UINT32 Rsvd1:21;\r
548} NVME_ADMIN_GET_FEATURES;\r
549\r
550//\r
551// NvmExpress Admin Get Log Page Command\r
552//\r
553typedef struct {\r
554 //\r
555 // CDW 10\r
556 //\r
557 UINT32 Lid:8; /* Log Page Identifier */\r
558 #define LID_ERROR_INFO\r
559 #define LID_SMART_INFO\r
560 #define LID_FW_SLOT_INFO\r
561 UINT32 Rsvd1:8;\r
562 UINT32 Numd:12; /* Number of Dwords */\r
563 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
564} NVME_ADMIN_GET_LOG_PAGE;\r
565\r
566//\r
567// NvmExpress Admin Set Features Command\r
568//\r
569typedef struct {\r
570 //\r
571 // CDW 10\r
572 //\r
573 UINT32 Fid:8; /* Feature Identifier */\r
574 UINT32 Rsvd1:23;\r
575 UINT32 Sv:1; /* Save */\r
576} NVME_ADMIN_SET_FEATURES;\r
577\r
578//\r
579// NvmExpress Admin Format NVM Command\r
580//\r
581typedef struct {\r
582 //\r
583 // CDW 10\r
584 //\r
585 UINT32 Lbaf:4; /* LBA Format */\r
586 UINT32 Ms:1; /* Metadata Settings */\r
587 UINT32 Pi:3; /* Protection Information */\r
588 UINT32 Pil:1; /* Protection Information Location */\r
589 UINT32 Ses:3; /* Secure Erase Settings */\r
590 UINT32 Rsvd1:20;\r
591} NVME_ADMIN_FORMAT_NVM;\r
592\r
593//\r
594// NvmExpress Admin Security Receive Command\r
595//\r
596typedef struct {\r
597 //\r
598 // CDW 10\r
599 //\r
600 UINT32 Rsvd1:8;\r
601 UINT32 Spsp:16; /* SP Specific */\r
602 UINT32 Secp:8; /* Security Protocol */\r
603 //\r
604 // CDW 11\r
605 //\r
606 UINT32 Al; /* Allocation Length */\r
607} NVME_ADMIN_SECURITY_RECEIVE;\r
608\r
609//\r
610// NvmExpress Admin Security Send Command\r
611//\r
612typedef struct {\r
613 //\r
614 // CDW 10\r
615 //\r
616 UINT32 Rsvd1:8;\r
617 UINT32 Spsp:16; /* SP Specific */\r
618 UINT32 Secp:8; /* Security Protocol */\r
619 //\r
620 // CDW 11\r
621 //\r
622 UINT32 Tl; /* Transfer Length */\r
623} NVME_ADMIN_SECURITY_SEND;\r
624\r
625typedef union {\r
626 NVME_ADMIN_IDENTIFY Identify;\r
627 NVME_ADMIN_CRIOCQ CrIoCq;\r
628 NVME_ADMIN_CRIOSQ CrIoSq;\r
629 NVME_ADMIN_DEIOCQ DeIoCq;\r
630 NVME_ADMIN_DEIOSQ DeIoSq;\r
631 NVME_ADMIN_ABORT Abort;\r
632 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
633 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
634 NVME_ADMIN_GET_FEATURES GetFeatures;\r
635 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
636 NVME_ADMIN_SET_FEATURES SetFeatures;\r
637 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
638 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
639 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
640} NVME_ADMIN_CMD;\r
641\r
642typedef struct {\r
643 UINT32 Cdw10;\r
644 UINT32 Cdw11;\r
645 UINT32 Cdw12;\r
646 UINT32 Cdw13;\r
647 UINT32 Cdw14;\r
648 UINT32 Cdw15;\r
649} NVME_RAW;\r
650\r
651typedef union {\r
652 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
653 NVME_CMD Nvm; // Union of Nvm commands\r
654 NVME_RAW Raw;\r
655} NVME_PAYLOAD;\r
656\r
657//\r
658// Submission Queue\r
659//\r
660typedef struct {\r
661 //\r
662 // CDW 0, Common to all comnmands\r
663 //\r
664 UINT8 Opc; // Opcode\r
665 UINT8 Fuse:2; // Fused Operation\r
666 UINT8 Rsvd1:5;\r
667 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
668 UINT16 Cid; // Command Identifier\r
669\r
670 //\r
671 // CDW 1\r
672 //\r
673 UINT32 Nsid; // Namespace Identifier\r
674\r
675 //\r
676 // CDW 2,3\r
677 //\r
678 UINT64 Rsvd2;\r
679\r
680 //\r
681 // CDW 4,5\r
682 //\r
683 UINT64 Mptr; // Metadata Pointer\r
684\r
685 //\r
686 // CDW 6-9\r
687 //\r
688 UINT64 Prp[2]; // First and second PRP entries\r
689\r
690 NVME_PAYLOAD Payload;\r
691\r
692} NVME_SQ;\r
693\r
694//\r
695// Completion Queue\r
696//\r
697typedef struct {\r
698 //\r
699 // CDW 0\r
700 //\r
701 UINT32 Dword0;\r
702 //\r
703 // CDW 1\r
704 //\r
705 UINT32 Rsvd1;\r
706 //\r
707 // CDW 2\r
708 //\r
709 UINT16 Sqhd; // Submission Queue Head Pointer\r
710 UINT16 Sqid; // Submission Queue Identifier\r
711 //\r
712 // CDW 3\r
713 //\r
714 UINT16 Cid; // Command Identifier\r
715 UINT16 Pt:1; // Phase Tag\r
716 UINT16 Sc:8; // Status Code\r
717 UINT16 Sct:3; // Status Code Type\r
718 UINT16 Rsvd2:2;\r
719 UINT16 Mo:1; // More\r
720 UINT16 Dnr:1; // Retry\r
721} NVME_CQ;\r
722\r
723//\r
724// Nvm Express Admin cmd opcodes\r
725//\r
726#define NVME_ADMIN_CRIOSQ_OPC 1\r
727#define NVME_ADMIN_CRIOCQ_OPC 5\r
728#define NVME_ADMIN_IDENTIFY_OPC 6\r
729\r
730#define NVME_IO_FLUSH_OPC 0\r
731#define NVME_IO_WRITE_OPC 1\r
732#define NVME_IO_READ_OPC 2\r
733\r
734//\r
735// Offset from the beginning of private data queue buffer\r
736//\r
737#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r
738\r
739/**\r
740 Initialize the Nvm Express controller.\r
741\r
742 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
743\r
744 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r
745 @retval Others A device error occurred while initializing the controller.\r
746\r
747**/\r
748EFI_STATUS\r
749NvmeControllerInit (\r
750 IN NVME_CONTROLLER_PRIVATE_DATA *Private\r
751 );\r
752\r
753/**\r
754 Get identify controller data.\r
755\r
756 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
757 @param Buffer The buffer used to store the identify controller data.\r
758\r
759 @return EFI_SUCCESS Successfully get the identify controller data.\r
760 @return EFI_DEVICE_ERROR Fail to get the identify controller data.\r
761\r
762**/\r
763EFI_STATUS\r
764NvmeIdentifyController (\r
765 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
766 IN VOID *Buffer\r
767 );\r
768\r
769/**\r
770 Get specified identify namespace data.\r
771\r
772 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
773 @param NamespaceId The specified namespace identifier.\r
774 @param Buffer The buffer used to store the identify namespace data.\r
775\r
776 @return EFI_SUCCESS Successfully get the identify namespace data.\r
777 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r
778\r
779**/\r
780EFI_STATUS\r
781NvmeIdentifyNamespace (\r
782 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
783 IN UINT32 NamespaceId,\r
784 IN VOID *Buffer\r
785 );\r
786\r
787#pragma pack()\r
788\r
789#endif\r
790\r
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