MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h

   1 /** @file
   2   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
   3   NVM Express specification.
   4
   5   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _NVME_HCI_H_
  17 #define _NVME_HCI_H_
  18
  19 #define NVME_BAR                 0
  20
  21 //
  22 // controller register offsets
  23 //
  24 #define NVME_CAP_OFFSET          0x0000  // Controller Capabilities
  25 #define NVME_VER_OFFSET          0x0008  // Version
  26 #define NVME_INTMS_OFFSET        0x000c  // Interrupt Mask Set
  27 #define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear
  28 #define NVME_CC_OFFSET           0x0014  // Controller Configuration
  29 #define NVME_CSTS_OFFSET         0x001c  // Controller Status
  30 #define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes
  31 #define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address
  32 #define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address
  33 #define NVME_SQ0_OFFSET          0x1000  // Submission Queue 0 (admin) Tail Doorbell
  34 #define NVME_CQ0_OFFSET          0x1004  // Completion Queue 0 (admin) Head Doorbell
  35
  36 //
  37 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
  38 // Get the doorbell stride bit shift value from the controller capabilities.
  39 //
  40 #define NVME_SQTDBL_OFFSET(QID, DSTRD)    0x1000 + ((2 * (QID)) * (4 << (DSTRD)))       // Submission Queue y (NVM) Tail Doorbell
  41 #define NVME_CQHDBL_OFFSET(QID, DSTRD)    0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
  42
  43
  44 #pragma pack(1)
  45
  46 //
  47 // 3.1.1 Offset 00h: CAP - Controller Capabilities
  48 //
  49 typedef struct {
  50   UINT16 Mqes;      // Maximum Queue Entries Supported
  51   UINT8  Cqr:1;     // Contiguous Queues Required
  52   UINT8  Ams:2;     // Arbitration Mechanism Supported
  53   UINT8  Rsvd1:5;
  54   UINT8  To;        // Timeout
  55   UINT16 Dstrd:4;
  56   UINT16 Rsvd2:1;
  57   UINT16 Css:4;     // Command Sets Supported
  58   UINT16 Rsvd3:7;
  59   UINT8  Mpsmin:4;
  60   UINT8  Mpsmax:4;
  61   UINT8  Rsvd4;
  62 } NVME_CAP;
  63
  64 //
  65 // 3.1.2 Offset 08h: VS - Version
  66 //
  67 typedef struct {
  68   UINT16 Mnr;       // Minor version number
  69   UINT16 Mjr;       // Major version number
  70 } NVME_VER;
  71
  72 //
  73 // 3.1.5 Offset 14h: CC - Controller Configuration
  74 //
  75 typedef struct {
  76   UINT16 En:1;       // Enable
  77   UINT16 Rsvd1:3;
  78   UINT16 Css:3;      // Command Set Selected
  79   UINT16 Mps:4;      // Memory Page Size
  80   UINT16 Ams:3;      // Arbitration Mechanism Selected
  81   UINT16 Shn:2;      // Shutdown Notification
  82   UINT8  Iosqes:4;   // I/O Submission Queue Entry Size
  83   UINT8  Iocqes:4;   // I/O Completion Queue Entry Size
  84   UINT8  Rsvd2;
  85 } NVME_CC;
  86
  87 //
  88 // 3.1.6 Offset 1Ch: CSTS - Controller Status
  89 //
  90 typedef struct {
  91   UINT32 Rdy:1;      // Ready
  92   UINT32 Cfs:1;      // Controller Fatal Status
  93   UINT32 Shst:2;     // Shutdown Status
  94   UINT32 Nssro:1;    // NVM Subsystem Reset Occurred
  95   UINT32 Rsvd1:27;
  96 } NVME_CSTS;
  97
  98 //
  99 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
 100 //
 101 typedef struct {
 102   UINT16 Asqs:12;    // Submission Queue Size
 103   UINT16 Rsvd1:4;
 104   UINT16 Acqs:12;    // Completion Queue Size
 105   UINT16 Rsvd2:4;
 106 } NVME_AQA;
 107
 108 //
 109 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
 110 //
 111 typedef struct {
 112   UINT64 Rsvd1:12;
 113   UINT64 Asqb:52;    // Admin Submission Queue Base Address
 114 } NVME_ASQ;
 115
 116 //
 117 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
 118 //
 119 typedef struct {
 120   UINT64 Rsvd1:12;
 121   UINT64 Acqb:52;    // Admin Completion Queue Base Address
 122 } NVME_ACQ;
 123
 124 //
 125 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
 126 //
 127 typedef struct {
 128   UINT16 Sqt;
 129   UINT16 Rsvd1;
 130 } NVME_SQTDBL;
 131
 132 //
 133 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
 134 //
 135 typedef struct {
 136   UINT16 Cqh;
 137   UINT16 Rsvd1;
 138 } NVME_CQHDBL;
 139
 140 //
 141 // NVM command set structures
 142 //
 143 // Read Command
 144 //
 145 typedef struct {
 146   //
 147   // CDW 10, 11
 148   //
 149   UINT64 Slba;                /* Starting Sector Address */
 150   //
 151   // CDW 12
 152   //
 153   UINT16 Nlb;                 /* Number of Sectors */
 154   UINT16 Rsvd1:10;
 155   UINT16 Prinfo:4;            /* Protection Info Check */
 156   UINT16 Fua:1;               /* Force Unit Access */
 157   UINT16 Lr:1;                /* Limited Retry */
 158   //
 159   // CDW 13
 160   //
 161   UINT32 Af:4;                /* Access Frequency */
 162   UINT32 Al:2;                /* Access Latency */
 163   UINT32 Sr:1;                /* Sequential Request */
 164   UINT32 In:1;                /* Incompressible */
 165   UINT32 Rsvd2:24;
 166   //
 167   // CDW 14
 168   //
 169   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 170   //
 171   // CDW 15
 172   //
 173   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 174   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 175 } NVME_READ;
 176
 177 //
 178 // Write Command
 179 //
 180 typedef struct {
 181   //
 182   // CDW 10, 11
 183   //
 184   UINT64 Slba;                /* Starting Sector Address */
 185   //
 186   // CDW 12
 187   //
 188   UINT16 Nlb;                 /* Number of Sectors */
 189   UINT16 Rsvd1:10;
 190   UINT16 Prinfo:4;            /* Protection Info Check */
 191   UINT16 Fua:1;               /* Force Unit Access */
 192   UINT16 Lr:1;                /* Limited Retry */
 193   //
 194   // CDW 13
 195   //
 196   UINT32 Af:4;                /* Access Frequency */
 197   UINT32 Al:2;                /* Access Latency */
 198   UINT32 Sr:1;                /* Sequential Request */
 199   UINT32 In:1;                /* Incompressible */
 200   UINT32 Rsvd2:24;
 201   //
 202   // CDW 14
 203   //
 204   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 205   //
 206   // CDW 15
 207   //
 208   UINT16 Lbat;                /* Logical Block Application Tag */
 209   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 210 } NVME_WRITE;
 211
 212 //
 213 // Flush
 214 //
 215 typedef struct {
 216   //
 217   // CDW 10
 218   //
 219   UINT32 Flush;               /* Flush */
 220 } NVME_FLUSH;
 221
 222 //
 223 // Write Uncorrectable command
 224 //
 225 typedef struct {
 226   //
 227   // CDW 10, 11
 228   //
 229   UINT64 Slba;                /* Starting LBA */
 230   //
 231   // CDW 12
 232   //
 233   UINT32 Nlb:16;              /* Number of  Logical Blocks */
 234   UINT32 Rsvd1:16;
 235 } NVME_WRITE_UNCORRECTABLE;
 236
 237 //
 238 // Write Zeroes command
 239 //
 240 typedef struct {
 241   //
 242   // CDW 10, 11
 243   //
 244   UINT64 Slba;                /* Starting LBA */
 245   //
 246   // CDW 12
 247   //
 248   UINT16 Nlb;                 /* Number of Logical Blocks */
 249   UINT16 Rsvd1:10;
 250   UINT16 Prinfo:4;            /* Protection Info Check */
 251   UINT16 Fua:1;               /* Force Unit Access */
 252   UINT16 Lr:1;                /* Limited Retry */
 253   //
 254   // CDW 13
 255   //
 256   UINT32 Rsvd2;
 257   //
 258   // CDW 14
 259   //
 260   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 261   //
 262   // CDW 15
 263   //
 264   UINT16 Lbat;                /* Logical Block Application Tag */
 265   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 266 } NVME_WRITE_ZEROES;
 267
 268 //
 269 // Compare command
 270 //
 271 typedef struct {
 272   //
 273   // CDW 10, 11
 274   //
 275   UINT64 Slba;                /* Starting LBA */
 276   //
 277   // CDW 12
 278   //
 279   UINT16 Nlb;                 /* Number of Logical Blocks */
 280   UINT16 Rsvd1:10;
 281   UINT16 Prinfo:4;            /* Protection Info Check */
 282   UINT16 Fua:1;               /* Force Unit Access */
 283   UINT16 Lr:1;                /* Limited Retry */
 284   //
 285   // CDW 13
 286   //
 287   UINT32 Rsvd2;
 288   //
 289   // CDW 14
 290   //
 291   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 292   //
 293   // CDW 15
 294   //
 295   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 296   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 297 } NVME_COMPARE;
 298
 299 typedef union {
 300   NVME_READ                   Read;
 301   NVME_WRITE                  Write;
 302   NVME_FLUSH                  Flush;
 303   NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;
 304   NVME_WRITE_ZEROES           WriteZeros;
 305   NVME_COMPARE                Compare;
 306 } NVME_CMD;
 307
 308 typedef struct {
 309   UINT16 Mp;                /* Maximum Power */
 310   UINT8  Rsvd1;             /* Reserved as of Nvm Express 1.1 Spec */
 311   UINT8  Mps:1;             /* Max Power Scale */
 312   UINT8  Nops:1;            /* Non-Operational State */
 313   UINT8  Rsvd2:6;           /* Reserved as of Nvm Express 1.1 Spec */
 314   UINT32 Enlat;             /* Entry Latency */
 315   UINT32 Exlat;             /* Exit Latency */
 316   UINT8  Rrt:5;             /* Relative Read Throughput */
 317   UINT8  Rsvd3:3;           /* Reserved as of Nvm Express 1.1 Spec */
 318   UINT8  Rrl:5;             /* Relative Read Leatency */
 319   UINT8  Rsvd4:3;           /* Reserved as of Nvm Express 1.1 Spec */
 320   UINT8  Rwt:5;             /* Relative Write Throughput */
 321   UINT8  Rsvd5:3;           /* Reserved as of Nvm Express 1.1 Spec */
 322   UINT8  Rwl:5;             /* Relative Write Leatency */
 323   UINT8  Rsvd6:3;           /* Reserved as of Nvm Express 1.1 Spec */
 324   UINT8  Rsvd7[16];         /* Reserved as of Nvm Express 1.1 Spec */
 325 } NVME_PSDESCRIPTOR;
 326
 327 //
 328 //  Identify Controller Data
 329 //
 330 typedef struct {
 331   //
 332   // Controller Capabilities and Features 0-255
 333   //
 334   UINT16 Vid;                 /* PCI Vendor ID */
 335   UINT16 Ssvid;               /* PCI sub-system vendor ID */
 336   UINT8  Sn[20];              /* Produce serial number */
 337
 338   UINT8  Mn[40];              /* Proeduct model number */
 339   UINT8  Fr[8];               /* Firmware Revision */
 340   UINT8  Rab;                 /* Recommended Arbitration Burst */
 341   UINT8  Ieee_oiu[3];         /* Organization Unique Identifier */
 342   UINT8  Cmic;                /* Multi-interface Capabilities */
 343   UINT8  Mdts;                /* Maximum Data Transfer Size */
 344   UINT8  Cntlid[2];           /* Controller ID */
 345   UINT8  Rsvd1[176];          /* Reserved as of Nvm Express 1.1 Spec */
 346   //
 347   // Admin Command Set Attributes
 348   //
 349   UINT16 Oacs;                /* Optional Admin Command Support */
 350   UINT8  Acl;                 /* Abort Command Limit */
 351   UINT8  Aerl;                /* Async Event Request Limit */
 352   UINT8  Frmw;                /* Firmware updates */
 353   UINT8  Lpa;                 /* Log Page Attributes */
 354   UINT8  Elpe;                /* Error Log Page Entries */
 355   UINT8  Npss;                /* Number of Power States Support */
 356   UINT8  Avscc;               /* Admin Vendor Specific Command Configuration */
 357   UINT8  Apsta;               /* Autonomous Power State Transition Attributes */
 358   UINT8  Rsvd2[246];          /* Reserved as of Nvm Express 1.1 Spec */
 359   //
 360   // NVM Command Set Attributes
 361   //
 362   UINT8  Sqes;                /* Submission Queue Entry Size */
 363   UINT8  Cqes;                /* Completion Queue Entry Size */
 364   UINT16 Rsvd3;               /* Reserved as of Nvm Express 1.1 Spec */
 365   UINT32 Nn;                  /* Number of Namespaces */
 366   UINT16 Oncs;                /* Optional NVM Command Support */
 367   UINT16 Fuses;               /* Fused Operation Support */
 368   UINT8  Fna;                 /* Format NVM Attributes */
 369   UINT8  Vwc;                 /* Volatile Write Cache */
 370   UINT16 Awun;                /* Atomic Write Unit Normal */
 371   UINT16 Awupf;               /* Atomic Write Unit Power Fail */
 372   UINT8  Nvscc;               /* NVM Vendor Specific Command Configuration */
 373   UINT8  Rsvd4;               /* Reserved as of Nvm Express 1.1 Spec */
 374   UINT16 Acwu;                /* Atomic Compare & Write Unit */
 375   UINT16 Rsvd5;               /* Reserved as of Nvm Express 1.1 Spec */
 376   UINT32 Sgls;                /* SGL Support  */
 377   UINT8  Rsvd6[164];          /* Reserved as of Nvm Express 1.1 Spec */
 378   //
 379   // I/O Command set Attributes
 380   //
 381   UINT8 Rsvd7[1344];          /* Reserved as of Nvm Express 1.1 Spec */
 382   //
 383   // Power State Descriptors
 384   //
 385   NVME_PSDESCRIPTOR PsDescriptor[32];
 386
 387   UINT8  VendorData[1024];    /* Vendor specific data */
 388 } NVME_ADMIN_CONTROLLER_DATA;
 389
 390 typedef struct {
 391   UINT16 Ms;                /* Metadata Size */
 392   UINT8  Lbads;             /* LBA Data Size */
 393   UINT8  Rp:2;              /* Relative Performance */
 394     #define LBAF_RP_BEST      00b
 395     #define LBAF_RP_BETTER    01b
 396     #define LBAF_RP_GOOD      10b
 397     #define LBAF_RP_DEGRADED  11b
 398   UINT8  Rsvd1:6;           /* Reserved as of Nvm Express 1.1 Spec */
 399 } NVME_LBAFORMAT;
 400
 401 //
 402 // Identify Namespace Data
 403 //
 404 typedef struct {
 405   //
 406   // NVM Command Set Specific
 407   //
 408   UINT64 Nsze;                /* Namespace Size (total number of blocks in formatted namespace) */
 409   UINT64 Ncap;                /* Namespace Capacity (max number of logical blocks) */
 410   UINT64 Nuse;                /* Namespace Utilization */
 411   UINT8  Nsfeat;              /* Namespace Features */
 412   UINT8  Nlbaf;               /* Number of LBA Formats */
 413   UINT8  Flbas;               /* Formatted LBA size */
 414   UINT8  Mc;                  /* Metadata Capabilities */
 415   UINT8  Dpc;                 /* End-to-end Data Protection capabilities */
 416   UINT8  Dps;                 /* End-to-end Data Protection Type Settings */
 417   UINT8  Nmic;                /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
 418   UINT8  Rescap;              /* Reservation Capabilities */
 419   UINT8  Rsvd1[88];           /* Reserved as of Nvm Express 1.1 Spec */
 420   UINT64 Eui64;               /* IEEE Extended Unique Identifier */
 421   //
 422   // LBA Format
 423   //
 424   NVME_LBAFORMAT LbaFormat[16];
 425
 426   UINT8 Rsvd2[192];           /* Reserved as of Nvm Express 1.1 Spec */
 427   UINT8 VendorData[3712];     /* Vendor specific data */
 428 } NVME_ADMIN_NAMESPACE_DATA;
 429
 430 //
 431 // NvmExpress Admin Identify Cmd
 432 //
 433 typedef struct {
 434   //
 435   // CDW 10
 436   //
 437   UINT32 Cns:2;
 438   UINT32 Rsvd1:30;
 439 } NVME_ADMIN_IDENTIFY;
 440
 441 //
 442 // NvmExpress Admin Create I/O Completion Queue
 443 //
 444 typedef struct {
 445   //
 446   // CDW 10
 447   //
 448   UINT32 Qid:16;              /* Queue Identifier */
 449   UINT32 Qsize:16;            /* Queue Size */
 450
 451   //
 452   // CDW 11
 453   //
 454   UINT32 Pc:1;                /* Physically Contiguous */
 455   UINT32 Ien:1;               /* Interrupts Enabled */
 456   UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */
 457   UINT32 Iv:16;               /* Interrupt Vector */
 458 } NVME_ADMIN_CRIOCQ;
 459
 460 //
 461 // NvmExpress Admin Create I/O Submission Queue
 462 //
 463 typedef struct {
 464   //
 465   // CDW 10
 466   //
 467   UINT32 Qid:16;              /* Queue Identifier */
 468   UINT32 Qsize:16;            /* Queue Size */
 469
 470   //
 471   // CDW 11
 472   //
 473   UINT32 Pc:1;                /* Physically Contiguous */
 474   UINT32 Qprio:2;             /* Queue Priority */
 475   UINT32 Rsvd1:13;            /* Reserved as of Nvm Express 1.1 Spec */
 476   UINT32 Cqid:16;             /* Completion Queue ID */
 477 } NVME_ADMIN_CRIOSQ;
 478
 479 //
 480 // NvmExpress Admin Delete I/O Completion Queue
 481 //
 482 typedef struct {
 483   //
 484   // CDW 10
 485   //
 486   UINT16 Qid;
 487   UINT16 Rsvd1;
 488 } NVME_ADMIN_DEIOCQ;
 489
 490 //
 491 // NvmExpress Admin Delete I/O Submission Queue
 492 //
 493 typedef struct {
 494   //
 495   // CDW 10
 496   //
 497   UINT16 Qid;
 498   UINT16 Rsvd1;
 499 } NVME_ADMIN_DEIOSQ;
 500
 501 //
 502 // NvmExpress Admin Abort Command
 503 //
 504 typedef struct {
 505   //
 506   // CDW 10
 507   //
 508   UINT32 Sqid:16;             /* Submission Queue identifier */
 509   UINT32 Cid:16;              /* Command Identifier */
 510 } NVME_ADMIN_ABORT;
 511
 512 //
 513 // NvmExpress Admin Firmware Activate Command
 514 //
 515 typedef struct {
 516   //
 517   // CDW 10
 518   //
 519   UINT32 Fs:3;                /* Submission Queue identifier */
 520   UINT32 Aa:2;                /* Command Identifier */
 521   UINT32 Rsvd1:27;
 522 } NVME_ADMIN_FIRMWARE_ACTIVATE;
 523
 524 //
 525 // NvmExpress Admin Firmware Image Download Command
 526 //
 527 typedef struct {
 528   //
 529   // CDW 10
 530   //
 531   UINT32 Numd;                /* Number of Dwords */
 532   //
 533   // CDW 11
 534   //
 535   UINT32 Ofst;                /* Offset */
 536 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
 537
 538 //
 539 // NvmExpress Admin Get Features Command
 540 //
 541 typedef struct {
 542   //
 543   // CDW 10
 544   //
 545   UINT32 Fid:8;                /* Feature Identifier */
 546   UINT32 Sel:3;                /* Select */
 547   UINT32 Rsvd1:21;
 548 } NVME_ADMIN_GET_FEATURES;
 549
 550 //
 551 // NvmExpress Admin Get Log Page Command
 552 //
 553 typedef struct {
 554   //
 555   // CDW 10
 556   //
 557   UINT32 Lid:8;               /* Log Page Identifier */
 558     #define LID_ERROR_INFO
 559     #define LID_SMART_INFO
 560     #define LID_FW_SLOT_INFO
 561   UINT32 Rsvd1:8;
 562   UINT32 Numd:12;             /* Number of Dwords */
 563   UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */
 564 } NVME_ADMIN_GET_LOG_PAGE;
 565
 566 //
 567 // NvmExpress Admin Set Features Command
 568 //
 569 typedef struct {
 570   //
 571   // CDW 10
 572   //
 573   UINT32 Fid:8;               /* Feature Identifier */
 574   UINT32 Rsvd1:23;
 575   UINT32 Sv:1;                /* Save */
 576 } NVME_ADMIN_SET_FEATURES;
 577
 578 //
 579 // NvmExpress Admin Format NVM Command
 580 //
 581 typedef struct {
 582   //
 583   // CDW 10
 584   //
 585   UINT32 Lbaf:4;              /* LBA Format */
 586   UINT32 Ms:1;                /* Metadata Settings */
 587   UINT32 Pi:3;                /* Protection Information */
 588   UINT32 Pil:1;               /* Protection Information Location */
 589   UINT32 Ses:3;               /* Secure Erase Settings */
 590   UINT32 Rsvd1:20;
 591 } NVME_ADMIN_FORMAT_NVM;
 592
 593 //
 594 // NvmExpress Admin Security Receive Command
 595 //
 596 typedef struct {
 597   //
 598   // CDW 10
 599   //
 600   UINT32 Rsvd1:8;
 601   UINT32 Spsp:16;             /* SP Specific */
 602   UINT32 Secp:8;              /* Security Protocol */
 603   //
 604   // CDW 11
 605   //
 606   UINT32 Al;                  /* Allocation Length */
 607 } NVME_ADMIN_SECURITY_RECEIVE;
 608
 609 //
 610 // NvmExpress Admin Security Send Command
 611 //
 612 typedef struct {
 613   //
 614   // CDW 10
 615   //
 616   UINT32 Rsvd1:8;
 617   UINT32 Spsp:16;             /* SP Specific */
 618   UINT32 Secp:8;              /* Security Protocol */
 619   //
 620   // CDW 11
 621   //
 622   UINT32 Tl;                  /* Transfer Length */
 623 } NVME_ADMIN_SECURITY_SEND;
 624
 625 typedef union {
 626   NVME_ADMIN_IDENTIFY                   Identify;
 627   NVME_ADMIN_CRIOCQ                     CrIoCq;
 628   NVME_ADMIN_CRIOSQ                     CrIoSq;
 629   NVME_ADMIN_DEIOCQ                     DeIoCq;
 630   NVME_ADMIN_DEIOSQ                     DeIoSq;
 631   NVME_ADMIN_ABORT                      Abort;
 632   NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;
 633   NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;
 634   NVME_ADMIN_GET_FEATURES               GetFeatures;
 635   NVME_ADMIN_GET_LOG_PAGE               GetLogPage;
 636   NVME_ADMIN_SET_FEATURES               SetFeatures;
 637   NVME_ADMIN_FORMAT_NVM                 FormatNvm;
 638   NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;
 639   NVME_ADMIN_SECURITY_SEND              SecuritySend;
 640 } NVME_ADMIN_CMD;
 641
 642 typedef struct {
 643   UINT32 Cdw10;
 644   UINT32 Cdw11;
 645   UINT32 Cdw12;
 646   UINT32 Cdw13;
 647   UINT32 Cdw14;
 648   UINT32 Cdw15;
 649 } NVME_RAW;
 650
 651 typedef union {
 652   NVME_ADMIN_CMD Admin;   // Union of Admin commands
 653   NVME_CMD       Nvm;     // Union of Nvm commands
 654   NVME_RAW       Raw;
 655 } NVME_PAYLOAD;
 656
 657 //
 658 // Submission Queue
 659 //
 660 typedef struct {
 661   //
 662   // CDW 0, Common to all comnmands
 663   //
 664   UINT8  Opc;               // Opcode
 665   UINT8  Fuse:2;            // Fused Operation
 666   UINT8  Rsvd1:5;
 667   UINT8  Psdt:1;            // PRP or SGL for Data Transfer
 668   UINT16 Cid;               // Command Identifier
 669
 670   //
 671   // CDW 1
 672   //
 673   UINT32 Nsid;              // Namespace Identifier
 674
 675   //
 676   // CDW 2,3
 677   //
 678   UINT64 Rsvd2;
 679
 680   //
 681   // CDW 4,5
 682   //
 683   UINT64 Mptr;              // Metadata Pointer
 684
 685   //
 686   // CDW 6-9
 687   //
 688   UINT64 Prp[2];            // First and second PRP entries
 689
 690   NVME_PAYLOAD Payload;
 691
 692 } NVME_SQ;
 693
 694 //
 695 // Completion Queue
 696 //
 697 typedef struct {
 698   //
 699   // CDW 0
 700   //
 701   UINT32 Dword0;
 702   //
 703   // CDW 1
 704   //
 705   UINT32 Rsvd1;
 706   //
 707   // CDW 2
 708   //
 709   UINT16 Sqhd;              // Submission Queue Head Pointer
 710   UINT16 Sqid;              // Submission Queue Identifier
 711   //
 712   // CDW 3
 713   //
 714   UINT16 Cid;               // Command Identifier
 715   UINT16 Pt:1;              // Phase Tag
 716   UINT16 Sc:8;              // Status Code
 717   UINT16 Sct:3;             // Status Code Type
 718   UINT16 Rsvd2:2;
 719   UINT16 Mo:1;              // More
 720   UINT16 Dnr:1;             // Retry
 721 } NVME_CQ;
 722
 723 //
 724 // Nvm Express Admin cmd opcodes
 725 //
 726 #define NVME_ADMIN_CRIOSQ_OPC                1
 727 #define NVME_ADMIN_CRIOCQ_OPC                5
 728 #define NVME_ADMIN_IDENTIFY_OPC              6
 729
 730 #define NVME_IO_FLUSH_OPC                    0
 731 #define NVME_IO_WRITE_OPC                    1
 732 #define NVME_IO_READ_OPC                     2
 733
 734 //
 735 // Offset from the beginning of private data queue buffer
 736 //
 737 #define NVME_ASQ_BUF_OFFSET                  EFI_PAGE_SIZE
 738
 739 /**
 740   Initialize the Nvm Express controller.
 741
 742   @param[in] Private                 The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
 743
 744   @retval EFI_SUCCESS                The NVM Express Controller is initialized successfully.
 745   @retval Others                     A device error occurred while initializing the controller.
 746
 747 **/
 748 EFI_STATUS
 749 NvmeControllerInit (
 750   IN NVME_CONTROLLER_PRIVATE_DATA    *Private
 751   );
 752
 753 /**
 754   Get identify controller data.
 755
 756   @param  Private          The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
 757   @param  Buffer           The buffer used to store the identify controller data.
 758
 759   @return EFI_SUCCESS      Successfully get the identify controller data.
 760   @return EFI_DEVICE_ERROR Fail to get the identify controller data.
 761
 762 **/
 763 EFI_STATUS
 764 NvmeIdentifyController (
 765   IN NVME_CONTROLLER_PRIVATE_DATA       *Private,
 766   IN VOID                               *Buffer
 767   );
 768
 769 /**
 770   Get specified identify namespace data.
 771
 772   @param  Private          The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
 773   @param  NamespaceId      The specified namespace identifier.
 774   @param  Buffer           The buffer used to store the identify namespace data.
 775
 776   @return EFI_SUCCESS      Successfully get the identify namespace data.
 777   @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
 778
 779 **/
 780 EFI_STATUS
 781 NvmeIdentifyNamespace (
 782   IN NVME_CONTROLLER_PRIVATE_DATA      *Private,
 783   IN UINT32                            NamespaceId,
 784   IN VOID                              *Buffer
 785   );
 786
 787 #pragma pack()
 788
 789 #endif
 790