MdeModulePkg/PciBus: Revert "disable all BME when entering RT"

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciDeviceSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 25387bd257c7707da4127a97906189d14a64c4f0..97bb971a5966a2d869d8da42b47cb4e5be386f27 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -1,8 +1,8 @@
 /** @file\r
   Supporting functions implementaion for PCI devices management.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -215,10 +215,6 @@ RegisterPciDevice (
   EFI_PCI_IO_PROTOCOL *PciIo;\r
   UINT8               Data8;\r
   BOOLEAN             HasEfiImage;\r
-  PCI_IO_DEVICE       *ParrentPciIoDevice;\r
-  EFI_PCI_IO_PROTOCOL *ParrentPciIo;\r
-  UINT16              Data16;\r
-  UINT32              Data32;\r
 \r
   //\r
   // Install the pciio protocol, device path protocol\r
@@ -255,35 +251,7 @@ RegisterPciDevice (
   PciIo = &(PciIoDevice->PciIo);\r
   Data8 = PCI_INT_LINE_UNKNOWN;\r
   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);\r
-  \r
-  //\r
-  // PCI-IOV programming\r
-  //\r
-  if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&\r
-      (PciIoDevice->SrIovCapabilityOffset != 0)) {\r
-    //\r
-    // Check its parrent ARI forwarding capability\r
-    //\r
-    ParrentPciIoDevice = PciIoDevice->Parent;\r
-    ParrentPciIo = &(ParrentPciIoDevice->PciIo);\r
-    ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);\r
-    if (Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {\r
-      //\r
-      // ARI forward support in bridge, so enable it.\r
-      //\r
-      ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);\r
-      Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;\r
-      ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);\r
-\r
-      //\r
-      // Set ARI Capable Hierarchy for device\r
-      //\r
-      PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);\r
-      Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);\r
-    }\r
-  }\r
-  \r
+ \r
   //\r
   // Process OpRom\r
   //\r
@@ -300,6 +268,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize\r
                                        );\r
       if (!EFI_ERROR (Status)) {\r
+        PciIoDevice->EmbeddedRom    = FALSE;\r
         PciIoDevice->RomSize        = PlatformOpRomSize;\r
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;\r
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
@@ -313,7 +282,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,\r
           PciIoDevice->DeviceNumber,\r
           PciIoDevice->FunctionNumber,\r
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,\r
+          PciIoDevice->PciIo.RomImage,\r
           PciIoDevice->PciIo.RomSize\r
           );\r
       }\r
@@ -325,6 +294,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize\r
                                        );\r
       if (!EFI_ERROR (Status)) {\r
+        PciIoDevice->EmbeddedRom    = FALSE;\r
         PciIoDevice->RomSize        = PlatformOpRomSize;\r
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;\r
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;\r
@@ -338,7 +308,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,\r
           PciIoDevice->DeviceNumber,\r
           PciIoDevice->FunctionNumber,\r
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,\r
+          PciIoDevice->PciIo.RomImage,\r
           PciIoDevice->PciIo.RomSize\r
           );\r
       }   \r
@@ -726,7 +696,7 @@ StartPciDevicesOnBridge (
       //\r
       // If it is a PPB\r
       //\r
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {\r
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
         Status = StartPciDevicesOnBridge (\r
                    Controller,\r
                    PciIoDevice,\r
@@ -741,7 +711,12 @@ StartPciDevicesOnBridge (
                              0,\r
                              &Supports\r
                              );\r
-        Supports &= EFI_PCI_DEVICE_ENABLE;\r
+        //\r
+        // By default every bridge's IO and MMIO spaces are enabled.\r
+        // Bridge's Bus Master will be enabled when any device behind it requests\r
+        // to enable Bus Master.\r
+        //\r
+        Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
         PciIoDevice->PciIo.Attributes (\r
                              &(PciIoDevice->PciIo),\r
                              EfiPciIoAttributeOperationEnable,\r
@@ -778,7 +753,7 @@ StartPciDevicesOnBridge (
         (*NumberOfChildren)++;\r
       }\r
 \r
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {\r
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
         Status = StartPciDevicesOnBridge (\r
                    Controller,\r
                    PciIoDevice,\r
@@ -793,7 +768,12 @@ StartPciDevicesOnBridge (
                              0,\r
                              &Supports\r
                              );\r
-        Supports &= EFI_PCI_DEVICE_ENABLE;\r
+        //\r
+        // By default every bridge's IO and MMIO spaces are enabled.\r
+        // Bridge's Bus Master will be enabled when any device behind it requests\r
+        // to enable Bus Master.\r
+        //\r
+        Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
         PciIoDevice->PciIo.Attributes (\r
                              &(PciIoDevice->PciIo),\r
                              EfiPciIoAttributeOperationEnable,\r